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Thu, 21 Aug 2025 23:35:29 -0700 Date: Thu, 21 Aug 2025 23:35:27 -0700 From: Nicolin Chen To: Jason Gunthorpe CC: Ethan Zhao , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v3 5/5] pci: Suspend iommu function prior to resetting a device Message-ID: References: <3749cd6a1430ac36d1af1fadaa4d90ceffef9c62.1754952762.git.nicolinc@nvidia.com> <550635db-00ce-410e-add0-77c1a75adb11@gmail.com> <20250821130741.GL802098@nvidia.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20250821130741.GL802098@nvidia.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000252A1:EE_|SA1PR12MB6773:EE_ X-MS-Office365-Filtering-Correlation-Id: cca042d2-1c0e-4496-2be8-08dde1462254 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|36860700013|82310400026|1800799024; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2025 06:35:49.5128 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cca042d2-1c0e-4496-2be8-08dde1462254 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000252A1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6773 On Thu, Aug 21, 2025 at 10:07:41AM -0300, Jason Gunthorpe wrote: > On Tue, Aug 19, 2025 at 02:59:07PM -0700, Nicolin Chen wrote: > > c) multiple pci_devs with their own RIDs > > > > In this case, either FLR or IOMMU only resets the PF. That > > being said, VFs might be affected since PF is resetting? > > If there is an issue, I don't see it coming from the IOMMU- > > level reset.. > > It would still allow the ATS issue from the VF side. The VF could be > pushing an invalidation during the PF reset that will get clobbered. > > I haven't fully checked but I think Linux doesn't really (easially?) > allow resetting a PF while a VF is present... Hmm, what if the PF encountered some fault? Does Linux have a choice not to reset PF? > Arguably if the PF is reset the VFs should have their translations > blocked too. Yea, that sounds plausible to me. But, prior to that (an IOMMU-level reset), should VFs be first reset at the PCI level? Thanks Nicolin