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Thu, 28 Aug 2025 13:01:54 -0700 (PDT) Received: from localhost ([2a00:79e0:2e14:7:2893:df0f:26ec:df00]) by smtp.gmail.com with UTF8SMTPSA id d9443c01a7336-24905da3be1sm3479885ad.69.2025.08.28.13.01.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 28 Aug 2025 13:01:53 -0700 (PDT) Date: Thu, 28 Aug 2025 13:01:51 -0700 From: Brian Norris To: manivannan.sadhasivam@oss.qualcomm.com Cc: Bjorn Helgaas , Mahesh J Salgaonkar , Oliver O'Halloran , Will Deacon , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Heiko Stuebner , Philipp Zabel , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-rockchip@lists.infradead.org, Niklas Cassel , Wilfred Mallawa , Krishna Chaitanya Chundru , Lukas Wunner Subject: Re: [PATCH v6 0/4] PCI: Add support for resetting the Root Ports in a platform specific way Message-ID: References: <20250715-pci-port-reset-v6-0-6f9cce94e7bb@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250715-pci-port-reset-v6-0-6f9cce94e7bb@oss.qualcomm.com> On Tue, Jul 15, 2025 at 07:51:03PM +0530, Manivannan Sadhasivam via B4 Relay wrote: > Hi, > > Currently, in the event of AER/DPC, PCI core will try to reset the slot (Root > Port) and its subordinate devices by invoking bridge control reset and FLR. But > in some cases like AER Fatal error, it might be necessary to reset the Root > Ports using the PCI host bridge drivers in a platform specific way (as indicated > by the TODO in the pcie_do_recovery() function in drivers/pci/pcie/err.c). > Otherwise, the PCI link won't be recovered successfully. > > So this series adds a new callback 'pci_host_bridge::reset_root_port' for the > host bridge drivers to reset the Root Port when a fatal error happens. > > Also, this series allows the host bridge drivers to handle PCI link down event > by resetting the Root Ports and recovering the bus. This is accomplished by the > help of the new 'pci_host_handle_link_down()' API. Host bridge drivers are > expected to call this API (preferrably from a threaded IRQ handler) with > relevant Root Port 'pci_dev' when a link down event is detected for the port. > The API will reuse the pcie_do_recovery() function to recover the link if AER > support is enabled, otherwise it will directly call the reset_root_port() > callback of the host bridge driver (if exists). > > For reference, I've modified the pcie-qcom driver to call > pci_host_handle_link_down() API with Root Port 'pci_dev' after receiving the > LINK_DOWN global_irq event and populated 'pci_host_bridge::reset_root_port()' > callback to reset the Root Port. Since the Qcom PCIe controllers support only > a single Root Port (slot) per controller instance, the API is going to be > invoked only once. For multi Root Port controllers, the controller driver is > expected to detect the Root Port that received the link down event and call > the pci_host_handle_link_down() API with 'pci_dev' of that Root Port. > > Testing > ------- > > I've lost access to my test setup now. So Krishna (Cced) will help with testing > on the Qcom platform and Wilfred or Niklas should be able to test it on Rockchip > platform. For the moment, this series is compile tested only. For the series: Tested-by: Brian Norris I've tested the whole thing on Qualcomm SC7280 Herobrine systems with NVMe. After adding a debugfs node to control toggling PERST, I can force the link to reset, and see it recover and resume NVMe traffic. I've tested the first two on Pixel phones, using a non-upstream DWC-based driver that I'm working on getting in better shape. (We've previously supported a custom link-error API setup instead.) I'd love to see this available upstream. Regards, Brian