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Sat, 08 Nov 2025 14:43:29 -0800 (PST) Date: Sat, 8 Nov 2025 19:43:17 -0300 From: Geraldo Nascimento To: Sebastian Reichel Cc: Shawn Lin , Ye Zhang , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski , Conor Dooley , Johan Jonker , linux-rockchip@lists.infradead.org Subject: Re: [PATCH] arm64: dts: rockchip: align bindings to PCIe spec Message-ID: References: <4b5ffcccfef2a61838aa563521672a171acb27b2.1762321976.git.geraldogabriel@gmail.com> <67b605b0-7046-448a-bc9b-d3ac56333809@rock-chips.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Sat, Nov 08, 2025 at 11:12:54PM +0100, Sebastian Reichel wrote: > Hi, Hi Sebastian, > > On Fri, Nov 07, 2025 at 11:01:04AM +0800, Shawn Lin wrote: > > + Ye Zhang > > > > 在 2025/11/07 星期五 10:43, Geraldo Nascimento 写道: > > > On Wed, Nov 05, 2025 at 04:56:36PM +0800, Shawn Lin wrote: > > > > 在 2025/11/05 星期三 16:18, Geraldo Nascimento 写道: > > > > > Hi Shawn, glad to hear from you. > > > > > > > > > > Perhaps the following change is better? It resolves the issue > > > > > without the added complication of open drain. After you questioned > > > > > if open drain is actually part of the spec, I remembered that > > > > > GPIO_OPEN_DRAIN is actually (GPIO_SINGLE_ENDED | GPIO_LINE_OPEN_DRAIN) > > > > > so I decided to test with just GPIO_SINGLE_ENDED and it works. > > > > > > Shawn, > > > > > > I quote from the PCIe Mini Card Electromechanical Specification Rev 1.2 > > > > > > "3.4.1. Logic Signal Requirements > > > > > > The 3.3V card logic levels for single-ended digital signals (WAKE#, > > > CLKREQ#, PERST#, and W_DISABLE#) are given in Table 3-7. [...]" > > > > > > So while you are correct that PERST# is most definitely not Open Drain, > > > there's evidence on the spec that defines this signal as Single-Ended. > > > > > > > This's true. But I couldn't find any user in dts using either > > GPIO_SINGLE_ENDED or GPIO_OPEN_DRAIN for PCIe PERST#. I'm curious > > how these two flags affect actual behavior of chips. Ye, could you > > please help check it? > > FWIW I assume single-ended in the spec means it's not differential > like all the highspeed signals on the PCIe connection. This says > nothing about open-drain, open-source or push-pull being used. The yes, I agree. It was an oversight on my part to assume open-drain on PERST# was part of the spec just because many cores implement it that way. Kudos to Shawn for correcting me. > kernel on the other hand has a very specific understanding of > GPIO_SINGLE_ENDED: > > if (flags & OF_GPIO_SINGLE_ENDED) { > if (flags & OF_GPIO_OPEN_DRAIN) > lflags |= GPIO_OPEN_DRAIN; > else > lflags |= GPIO_OPEN_SOURCE; > } > > I.e. it is the same as configuring open-source ;) Yup, I had noticed that. This works because the reset value of PMU GRF register PMUGRF_GPIO0B_P sets the relevant PERST# GPIO (GPIO0-12) on my board to pull-down, which can work with Open Source/Emitter. If we set the GPIO to Open Drain/Collector we must on the other hand set that pin to pull-up. Either way it works. I've been investigating why that GPIO isn't properly working as Push-Pull for my board (Rock PI N10) but so far I'm clueless. Thank you, Geraldo Nascimento > > Greetings, > > -- Sebastian