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Sun, 09 Nov 2025 15:58:00 -0800 (PST) Date: Sun, 9 Nov 2025 20:57:52 -0300 From: Geraldo Nascimento To: Dragan Simic Cc: Bjorn Helgaas , linux-rockchip@lists.infradead.org, Shawn Lin , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Heiko Stuebner , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski , Conor Dooley , Johan Jonker Subject: Re: [RFC PATCH 2/2] PCI: rockchip-host: drop wait on PERST# toggle Message-ID: References: <20251103181038.GA1814635@bhelgaas> <17220ae9-9e0e-cb0b-63bd-eaf9a6ed6411@manjaro.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <17220ae9-9e0e-cb0b-63bd-eaf9a6ed6411@manjaro.org> On Mon, Nov 10, 2025 at 12:51:49AM +0100, Dragan Simic wrote: > Hello Geraldo, > > On Wednesday, November 05, 2025 04:55 CET, Geraldo Nascimento wrote: > > I did some more testing, intrigued by why would a delay of more than > > 5 ms after the enablement of the power rails trigger failure in > > initial link-training. > > > > Something in my intuition kept telling me this was PERST# related, > > and so I followed that rabbit-hole. > > > > It seems the following change will allow the SSD to work with the > > Rockchip-IP PCIe core without any other changes. So it is purely > > a DT change and we are able to keep the mandatory 100ms delay > > after driving PERST# low, as well as the always-on/boot-on > > properties of the 3v3 power regulator. > > > > This time everything is within the PCIe spec AFAICT, PERST# indeed > > is an Open Drain signal, and indeed it does requires pull-up resistor > > to maintain the drive after driving it high. > > > > I'm still testing the overall stability of this, let's hope for the > > best! > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi > > index aa70776e898a..1c5afc0413bc 100644 > > --- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi > > +++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi > > @@ -383,13 +383,14 @@ &pcie_phy { > > }; > > > > &pcie0 { > > - ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>; > > + ep-gpios = <&gpio0 RK_PB4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; > > num-lanes = <4>; > > - pinctrl-0 = <&pcie_clkreqnb_cpm>; > > + pinctrl-0 = <&pcie_clkreqnb_cpm>, <&pcie_perst>; > > pinctrl-names = "default"; > > vpcie0v9-supply = <&vcca_0v9>; /* VCC_0V9_S0 */ > > vpcie1v8-supply = <&vcca_1v8>; /* VCC_1V8_S0 */ > > vpcie3v3-supply = <&vcc3v3_pcie>; > > + max-link-speed = <2>; > > FWIW, we shouldn't be enabling PCIe Gen2 here, because it's been > already disabled for the RK3399 due to unknown errata in the commit > 712fa1777207 ("arm64: dts: rockchip: add max-link-speed for rk3399", > 2016-12-16). It's perfectly reasonable to assume the same for the > RK3399Pro, which is basically RK3399 packaged together with RK1808, > AFAIK with no on-package interconnects. Hi Dragan! Thanks for the catch, you are correct. But in this case it was just for my tests and it crept in in the git diff. I wasn't really proposing to make that change. Thanks, Geraldo Nascimento