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smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Z2tMdDdx; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Z2tMdDdx" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8FDC2C116D0; Mon, 10 Nov 2025 12:41:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1762778494; bh=Eb3GSPNticXIxxLgS/f24j6ecx9A5x3T4N37cr98YT4=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=Z2tMdDdxgWlB1JhvhOXNoZalXUZXTgXjJZ5YGfP5lDf6dGcsq3XnFdsTNUiH0BcQ1 CPYNUhpucvOqLCZDrYMYz8ilGov8kmQDuo4yQdae5Wk2BpGWlhJicasIPuEeSczsG/ H75yEW/fXShEiB9bjWLwgxGTHZgpzuqQBIwGkcEn7R4tkNQgpHZlHrGEN4xuc7SvNA jTN+JKzQhJc4o5v9mnu7Qx4I+r/NBL0CGLGcJ0YiaGq6No944KsltQDb4uIcaeR3KK ba9YkW9rlcxG/5MYAsPohoGkC34XhEYCJzNl0q2/wQOPB4t0PFVHPeThxbFq/fFth1 gmc00AfZ4zT1w== Date: Mon, 10 Nov 2025 13:41:29 +0100 From: Niklas Cassel To: Shawn Lin Cc: FUKAUMI Naoki , Damien Le Moal , Anand Moon , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Dragan Simic , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Heiko Stuebner , mani@kernel.org Subject: Re: [RESEND] Re: [PATCH] PCI: dw-rockchip: Skip waiting for link up Message-ID: References: <55EB0E5F655F3AFC+136b89fd-98d4-42af-a99d-a0bb05cc93f3@radxa.com> <780a4209-f89f-43a9-9364-331d3b77e61e@rock-chips.com> <4487DA40249CC821+19232169-a096-4737-bc6a-5cec9592d65f@radxa.com> <363d6b4d-c999-43d4-866e-880ef7d0dec3@rock-chips.com> <0C31787C387488ED+fd39bfe6-0844-4a87-bf48-675dd6d6a2df@radxa.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Mon, Nov 10, 2025 at 01:34:41PM +0100, Niklas Cassel wrote: > @@ -672,15 +705,13 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) > if (!pp->use_linkup_irq) > /* Ignore errors, the link may come up later */ > dw_pcie_wait_for_link(pci); > - > - ret = pci_host_probe(bridge); > - if (ret) > - goto err_stop_link; > - > - if (pp->ops->post_init) > - pp->ops->post_init(pp); > - > - dwc_pcie_debugfs_init(pci, DW_PCIE_RC_TYPE); > + else > + /* > + * For platforms with Link Up IRQ, initial scan will be done > + * on first Link Up IRQ. > + */ > + if (dw_pcie_host_initial_scan(pp)) > + goto err_stop_link; Oops.. this condition was inverted, what I meant was: diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index e92513c5bda5..0e04c1d6d260 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -565,6 +565,39 @@ static int dw_pcie_host_get_resources(struct dw_pcie_rp *pp) return 0; } +static int dw_pcie_host_initial_scan(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct pci_host_bridge *bridge = pp->bridge; + int ret; + + ret = pci_host_probe(bridge); + if (ret) + return ret; + + if (pp->ops->post_init) + pp->ops->post_init(pp); + + dwc_pcie_debugfs_init(pci, DW_PCIE_RC_TYPE); + + return 0; +} + +void dw_pcie_handle_link_up_irq(struct dw_pcie_rp *pp) +{ + if (!pp->initial_linkup_irq_done) { + if (dw_pcie_host_initial_scan(pp)) { + //TODO: cleanup + } + pp->initial_linkup_irq_done = true; + } else { + /* Rescan the bus to enumerate endpoint devices */ + pci_lock_rescan_remove(); + pci_rescan_bus(pp->bridge->bus); + pci_unlock_rescan_remove(); + } +} + int dw_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -669,18 +702,17 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) * If there is no Link Up IRQ, we should not bypass the delay * because that would require users to manually rescan for devices. */ - if (!pp->use_linkup_irq) + if (!pp->use_linkup_irq) { /* Ignore errors, the link may come up later */ dw_pcie_wait_for_link(pci); - ret = pci_host_probe(bridge); - if (ret) - goto err_stop_link; - - if (pp->ops->post_init) - pp->ops->post_init(pp); - - dwc_pcie_debugfs_init(pci, DW_PCIE_RC_TYPE); + /* + * For platforms with Link Up IRQ, initial scan will be done + * on first Link Up IRQ. + */ + if (dw_pcie_host_initial_scan(pp)) + goto err_stop_link; + } return 0; diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index e995f692a1ec..a31bd93490dc 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -427,6 +427,7 @@ struct dw_pcie_rp { int msg_atu_index; struct resource *msg_res; bool use_linkup_irq; + bool initial_linkup_irq_done; struct pci_eq_presets presets; struct pci_config_window *cfg; bool ecam_enabled; @@ -807,6 +808,7 @@ void dw_pcie_msi_init(struct dw_pcie_rp *pp); int dw_pcie_msi_host_init(struct dw_pcie_rp *pp); void dw_pcie_free_msi(struct dw_pcie_rp *pp); int dw_pcie_setup_rc(struct dw_pcie_rp *pp); +void dw_pcie_handle_link_up_irq(struct dw_pcie_rp *pp); int dw_pcie_host_init(struct dw_pcie_rp *pp); void dw_pcie_host_deinit(struct dw_pcie_rp *pp); int dw_pcie_allocate_domains(struct dw_pcie_rp *pp); @@ -844,6 +846,9 @@ static inline int dw_pcie_setup_rc(struct dw_pcie_rp *pp) return 0; } +static inline void dw_pcie_handle_link_up_irq(struct dw_pcie_rp *pp) +{ } + static inline int dw_pcie_host_init(struct dw_pcie_rp *pp) { return 0; diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c index 8a882dcd1e4e..042e5845bdd6 100644 --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c @@ -468,10 +468,7 @@ static irqreturn_t rockchip_pcie_rc_sys_irq_thread(int irq, void *arg) if (rockchip_pcie_link_up(pci)) { msleep(PCIE_RESET_CONFIG_WAIT_MS); dev_dbg(dev, "Received Link up event. Starting enumeration!\n"); - /* Rescan the bus to enumerate endpoint devices */ - pci_lock_rescan_remove(); - pci_rescan_bus(pp->bridge->bus); - pci_unlock_rescan_remove(); + dw_pcie_handle_link_up_irq(pp); } }