From: Wolfram Sang <wsa+renesas@sang-engineering.com>
To: Claudiu <claudiu.beznea@tuxon.dev>
Cc: bhelgaas@google.com, lpieralisi@kernel.org,
kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org,
linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
linux-kernel@vger.kernel.org,
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Subject: Re: [PATCH v2 2/2] PCI: rzg3s-host: Drop the lock on RZG3S_PCI_MSIRS and RZG3S_PCI_PINTRCVIS
Date: Sat, 20 Dec 2025 09:24:33 +0100 [thread overview]
Message-ID: <aUZdQdXNDdZka-JU@shikoro> (raw)
In-Reply-To: <20251217111510.138848-3-claudiu.beznea.uj@bp.renesas.com>
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On Wed, Dec 17, 2025 at 01:15:10PM +0200, Claudiu wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
>
> The RZG3S_PCI_MSIRS and RZG3S_PCI_PINTRCVIS registers are of the R/W1C
> type. According to the RZ/G3S HW Manual, Rev. 1.10, chapter 34.2.1
> Register Type, R/W1C register bits are cleared to 0b by writing 1b, while
> writing 0b has no effect. Therefore, there is no need to take a lock
> around writes to these registers.
>
> Drop the locking.
>
> Along with this, add a note about the R/W1C register type to the register
> offset definitions.
>
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
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next prev parent reply other threads:[~2025-12-20 8:24 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-17 11:15 [PATCH v2 0/2] PCI: rzg3s-host: Cleanups Claudiu
2025-12-17 11:15 ` [PATCH v2 1/2] PCI: rzg3s-host: Use pci_generic_config_write() for the root bus Claudiu
2025-12-20 8:24 ` Wolfram Sang
2025-12-17 11:15 ` [PATCH v2 2/2] PCI: rzg3s-host: Drop the lock on RZG3S_PCI_MSIRS and RZG3S_PCI_PINTRCVIS Claudiu
2025-12-20 8:24 ` Wolfram Sang [this message]
2025-12-19 11:42 ` [PATCH v2 0/2] PCI: rzg3s-host: Cleanups Wolfram Sang
2025-12-19 17:21 ` Claudiu Beznea
2025-12-20 8:24 ` Wolfram Sang
2025-12-30 17:13 ` Manivannan Sadhasivam
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