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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-121725548b5sm105546648c88.17.2025.12.27.23.02.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Dec 2025 23:02:39 -0800 (PST) Date: Sat, 27 Dec 2025 23:02:37 -0800 From: Qiang Yu To: Manivannan Sadhasivam Cc: Bjorn Helgaas , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Jingoo Han , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: Re: [PATCH 3/5] PCI: dwc: Remove MSI/MSIX capability if iMSI-RX is used as MSI controller Message-ID: References: <20251109-remove_cap-v1-3-2208f46f4dc2@oss.qualcomm.com> <20251226213123.GA4141314@bhelgaas> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-Proofpoint-ORIG-GUID: -I9CTHiolkf0-bLeEl-mQr4G33SxvY9u X-Proofpoint-GUID: -I9CTHiolkf0-bLeEl-mQr4G33SxvY9u X-Authority-Analysis: v=2.4 cv=coiWUl4i c=1 sm=1 tr=0 ts=6950d611 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=rvI9OrrfPYhO3Jog6jQA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjI4MDA2MCBTYWx0ZWRfX3/LOU/c+eNA/ 6JHwcMIApqP6kzKJ2myFKtvCxpo11oBARwEtzWXHFJFQ9+WkAMTgij9nTufME5N6IxU2sjZU2uP f4ljQIVeDLd0Iyuls/S3CJ5tTY1Npeli2kryvrG+EyOmM6OFa6ovUwHRqXI88M6LvlPyO3xNXx0 LZfdfv52F1ySo210YD9D0asJ+hjNOiZzwmMtX6A7Yoz/OfQZ0Hh/raSvvx9oZP/oGD+53G+jAAv 7MhfcQYhbCA6jsUk7bZ6WRARKOArR5Tr+0/Iu3cQQxdEgbdgtnX/1EAwBoTPMoDHeI5gtgrLPrF eN2qRqcZOI1+AixBABqbGPfb1wJfGS8GiLEMTXbnW1lOYxKYmWCikJvdtTzji4rJ6rEHBpcKA/H mcdeJxUkO8TBxYJCG8kSD/74Vm06RQien+Skl1nejpr7nBlggmu6+w6kxYtPG26nQvDZNHZTv7f dtFakztdON1tQwYB1RA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-12-28_02,2025-12-26_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 malwarescore=0 phishscore=0 adultscore=0 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2512280060 On Sat, Dec 27, 2025 at 10:51:26AM +0530, Manivannan Sadhasivam wrote: > On Fri, Dec 26, 2025 at 03:31:23PM -0600, Bjorn Helgaas wrote: > > In subject, s/MSIX/MSI-X/ to match spec and other usage. > > > > On Sun, Nov 09, 2025 at 10:59:42PM -0800, Qiang Yu wrote: > > > Some platforms may not support ITS (Interrupt Translation Service) and > > > MBI (Message Based Interrupt), or there are not enough available empty SPI > > > lines for MBI, in which case the msi-map and msi-parent property will not > > > be provided in device tree node. For those cases, the DWC PCIe driver > > > defaults to using the iMSI-RX module as MSI controller. However, due to > > > DWC IP design, iMSI-RX cannot generate MSI interrupts for Root Ports even > > > when MSI is properly configured and supported as iMSI-RX will only monitor > > > and intercept incoming MSI TLPs from PCIe link, but the memory write > > > generated by Root Port are internal system bus transactions instead of > > > PCIe TLPs, so they are ignored. > > > > > > This leads to interrupts such as PME, AER from the Root Port not received > > > on the host and the users have to resort to workarounds such as passing > > > "pcie_pme=nomsi" cmdline parameter. > > > > This will be great, thanks a lot for working on this. This has been a > > long-standing irritation with this DWC IP. > > > > > To ensure reliable interrupt handling, remove MSI and MSI-X capabilities > > > from Root Ports when using iMSI-RX as MSI controller, which is indicated > > > by has_msi_ctrl == true. This forces a fallback to INTx interrupts, > > > eliminating the need for manual kernel command line workarounds. > > > > > > With this behavior: > > > - Platforms with ITS/MBI support use ITS/MBI MSI for interrupts from all > > > components. > > > - Platforms without ITS/MBI support fall back to INTx for Root Ports and > > > use iMSI-RX for other PCI devices. > > > > > > Signed-off-by: Qiang Yu > > > --- > > > drivers/pci/controller/dwc/pcie-designware-host.c | 10 ++++++++++ > > > 1 file changed, 10 insertions(+) > > > > > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > > > index 20c9333bcb1c4812e2fd96047a49944574df1e6f..3724aa7f9b356bfba33a6515e2c62a3170aef1e9 100644 > > > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > > > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > > > @@ -1083,6 +1083,16 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) > > > > > > dw_pcie_dbi_ro_wr_dis(pci); > > > > > > + /* > > > + * If iMSI-RX module is used as the MSI controller, remove MSI and > > > + * MSI-X capabilities from PCIe Root Ports to ensure fallback to INTx > > > + * interrupt handling. > > > + */ > > > + if (pp->has_msi_ctrl) { > > > + dw_pcie_remove_capability(pci, PCI_CAP_ID_MSI); > > > + dw_pcie_remove_capability(pci, PCI_CAP_ID_MSIX); > > > + } > > > > "has_msi_ctrl" doesn't seem like a good name here because there's no > > documentation about what it means, and "has_msi_ctrl" is completely > > generic while "iMSI-RX" is very specific. > > > > This predates my involvement with DWC drivers, but I guess it expands to 'has > internal MSI controller' and 'internal' probably means iMSI-RX. But I agree that > the naming could be improved to something like 'imsi_rx_available' or > 'has_imsi_rx'. I'll take a stab at it in a separate patch. > > > And apparently platforms with ITS/MBI *can* generate MSIs from Root > > Ports, but "has_msi_ctrl" would be false for them? This is really > > hard to read. > > > > Yes. > > > pp->has_msi_ctrl is set by qcom_pcie_ecam_host_init() and IIUC, for > > any platform that lacks .msi_init() and the "msi-parent" and "msi-map" > > properties. > > > > The qcom_pcie_ecam_host_init() case is weird because it looks like it > > abuses the pci_ecam_ops.init() callback to initialize MSI stuff, not > > ECAM stuff. Maybe that MSI init could be done in qcom_pcie_probe() > > right after it calls pci_host_common_ecam_create()? > > > > I think it should be possible to initialize MSI after > pci_host_common_ecam_create(). Let me fix *this* and above in a separate series. The qcom_pcie_ecam_host_init() is used by firmware-managed targets and the function unconditionally sets has_msi_ctrl = true without checking for "msi-parent" or "msi-map" properties in the device tree. So I think firmware should take care of removing MSI/MSIX cap. - Qiang Yu > > - Mani > > -- > மணிவண்ணன் சதாசிவம்