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Tue, 30 Dec 2025 01:45:44 -0800 (PST) Date: Tue, 30 Dec 2025 17:45:39 +0800 From: Inochi Amaoto To: Bjorn Helgaas , Inochi Amaoto Cc: Bjorn Helgaas , Chen Wang , Han Gao , Manivannan Sadhasivam , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Yixun Lan , Longbin Li Subject: Re: [PATCH 0/2] PCI/ASPM: Avoid L0s and L1 on Sophgo 2042/2044 PCIe Root Ports Message-ID: References: <20251225100530.1301625-1-inochiama@gmail.com> <20251226163031.GA4128882@bhelgaas> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20251226163031.GA4128882@bhelgaas> On Fri, Dec 26, 2025 at 10:30:31AM -0600, Bjorn Helgaas wrote: > On Thu, Dec 25, 2025 at 06:05:27PM +0800, Inochi Amaoto wrote: > > Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM > > states for devicetree platforms") force enable ASPM on all device tree > > platform, the SG2042/SG2044 PCIe Root Ports breaks as it advertises L0s > > and L1 capabilities without supporting it. > > > > Override the L0s and L1 Support advertised in Link Capabilities by the > > SG2042/SG2044 Root Ports so we don't try to enable those states. > > > > Inochi Amaoto (2): > > PCI/ASPM: Avoid L0s and L1 on Sophgo 2042 PCIe [1f1c:2042] Root Ports > > PCI/ASPM: Avoid L0s and L1 on Sophgo 2044 PCIe [1f1c:2044] Root Ports > > > > drivers/pci/quirks.c | 2 ++ > > include/linux/pci_ids.h | 2 ++ > > 2 files changed, 4 insertions(+) > > 1) Can somebody at Sophgo confirm that this is a hardware erratum? I > just want to make rule out some kind of OS bug in configuring L0s/L1. > Hi Bjorn, I have asked for the Sophgo staff, and they already confirmed this hardware errata. Regards, Inochi