[PATCH 0/9] PCI: endpoint differentiate between disabled and reserved BARs

[PATCH 0/9] PCI: endpoint differentiate between disabled and reserved BARs

[Niklas Cassel]

Hello all,

This series is written in response to the patch series from
Manikanta Maddireddy that was posted here:
https://lore.kernel.org/linux-pci/291dab65-3fa6-4fc8-90a2-4ad608ca015c@nvidia.com/T/#t

The reasons why I decided to post this a new series was because the series
above:

1) Adds PCI device and vendor specific code to
drivers/misc/pci_endpoint_test.c. We've worked hard to make sure that
device specific quirks/limitations are communicated via the Capabilities
register, so let's do the same for reserved BARs.

2) My review comment which suggested to convert all uses of BAR_RESERVED
to BAR_DISABLED (except for pci-keystone.c) was ignored.

3) Koichiro has posted a series that allows an EPC driver to define exactly
which hardware backed resources are provided in a BAR_RESERVED BAR. Yet,
this nice improvement was not incorporated. (While Mankata was part of the
discussion, he was not CC:d on the patches that actually implemented this.)

4) The selftests should return skip instead of silent success for a
reserved BAR.

5) As Mankata points out, but did not address, BAR_RESERVED is quite
ambiguous, so it is better to introduce a new BAR_64BIT_UPPER to more
clearly mark the upper part of a 64-bit BAR as this, rather than reuse
BAR_RESERVED.

6) It is possible to remove all the dw_pcie_ep_reset_bar() calls in the
DWC based glue drivers and move it to DWC common code.


Because of all of the above, I thought it was just easier to post a series
with all of the above addressed, as it seemed easier to just show what I
meant rather than to try to explain things with words.

The thing that is missing is to add a patch for pcie-tegra194.c which
converts the BARs to BAR_RESERVED.
Please see patch "PCI: dw-rockchip: Describe RK3588 BAR4 DMA ctrl window"
and do something similar to pcie-tegra194.c.

If we are missing some resources (right now we only have
PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO), then I think we should simple add that
(e.g. PCI_EPC_BAR_RSVD_MSIX).

Mankata, it would be nice if you could test this series, and if you could
provide a pcie-tegra194.c patch that adds the sizes of the eDMA regs +
MSI-X table in BAR_2 and BAR_4.


Kind regards,
Niklas


Koichiro Den (2):
  PCI: endpoint: Describe reserved subregions within BARs
  PCI: dw-rockchip: Describe RK3588 BAR4 DMA ctrl window

Niklas Cassel (7):
  PCI: endpoint: Introduce pci_epc_bar_type BAR_64BIT_UPPER
  PCI: endpoint: Introduce pci_epc_bar_type BAR_DISABLED
  PCI: dwc: Replace BAR_RESERVED with BAR_DISABLED in glue drivers
  PCI: dwc: Disable BARs in common code instead of in each glue driver
  PCI: endpoint: pci-epf-test: Advertise reserved BARs
  misc: pci_endpoint_test: Give reserved BARs a distinct error code
  selftests: pci_endpoint: Skip reserved BARs

 drivers/misc/pci_endpoint_test.c              | 32 ++++++++++++-
 drivers/pci/controller/dwc/pci-dra7xx.c       |  4 --
 drivers/pci/controller/dwc/pci-imx6.c         | 22 +++------
 .../pci/controller/dwc/pci-layerscape-ep.c    |  8 +---
 drivers/pci/controller/dwc/pcie-artpec6.c     |  4 --
 .../pci/controller/dwc/pcie-designware-ep.c   | 24 ++++++++++
 .../pci/controller/dwc/pcie-designware-plat.c | 10 -----
 drivers/pci/controller/dwc/pcie-dw-rockchip.c | 19 +++++---
 drivers/pci/controller/dwc/pcie-keembay.c     |  6 +--
 drivers/pci/controller/dwc/pcie-qcom-ep.c     | 14 +-----
 drivers/pci/controller/dwc/pcie-rcar-gen4.c   | 16 ++-----
 drivers/pci/controller/dwc/pcie-stm32-ep.c    | 10 -----
 drivers/pci/controller/dwc/pcie-tegra194.c    | 20 +++------
 drivers/pci/controller/dwc/pcie-uniphier-ep.c | 24 +++-------
 drivers/pci/controller/pcie-rcar-ep.c         |  6 +--
 drivers/pci/endpoint/functions/pci-epf-test.c | 24 ++++++++++
 drivers/pci/endpoint/pci-epc-core.c           |  6 ++-
 include/linux/pci-epc.h                       | 45 +++++++++++++++++--
 .../pci_endpoint/pci_endpoint_test.c          |  4 ++
 19 files changed, 173 insertions(+), 125 deletions(-)

-- 
2.53.0

[PATCH 1/9] PCI: endpoint: Introduce pci_epc_bar_type BAR_64BIT_UPPER

[Niklas Cassel]

Add a pci_epc_bar_type BAR_64BIT_UPPER to more clearly differentiate
BAR_64BIT_UPPER from BAR_RESERVED.

This BAR type will only be used for a BAR following a "only_64bit" BAR.

This makes the BAR description more clear, and the reader does no longer
need to check the BAR type for the preceding BAR to know how to interpret
the BAR type.

No functional changes.

Signed-off-by: Niklas Cassel <cassel@kernel.org>
---
 drivers/pci/controller/dwc/pci-layerscape-ep.c |  4 ++--
 drivers/pci/controller/dwc/pcie-keembay.c      |  6 +++---
 drivers/pci/controller/dwc/pcie-qcom-ep.c      |  4 ++--
 drivers/pci/controller/dwc/pcie-tegra194.c     |  2 +-
 drivers/pci/controller/dwc/pcie-uniphier-ep.c  | 10 +++++-----
 drivers/pci/controller/pcie-rcar-ep.c          |  6 +++---
 drivers/pci/endpoint/pci-epc-core.c            |  3 ++-
 include/linux/pci-epc.h                        |  5 ++++-
 8 files changed, 22 insertions(+), 18 deletions(-)

diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
index a4a800699f89..5a03a8f895f9 100644
--- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
+++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
@@ -251,9 +251,9 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)
 	pci->ops = pcie->drvdata->dw_pcie_ops;
 
 	ls_epc->bar[BAR_2].only_64bit = true;
-	ls_epc->bar[BAR_3].type = BAR_RESERVED;
+	ls_epc->bar[BAR_3].type = BAR_64BIT_UPPER;
 	ls_epc->bar[BAR_4].only_64bit = true;
-	ls_epc->bar[BAR_5].type = BAR_RESERVED;
+	ls_epc->bar[BAR_5].type = BAR_64BIT_UPPER;
 	ls_epc->linkup_notifier = true;
 
 	pcie->pci = pci;
diff --git a/drivers/pci/controller/dwc/pcie-keembay.c b/drivers/pci/controller/dwc/pcie-keembay.c
index 2666a9c3d67e..5a00b8cf5b53 100644
--- a/drivers/pci/controller/dwc/pcie-keembay.c
+++ b/drivers/pci/controller/dwc/pcie-keembay.c
@@ -313,11 +313,11 @@ static const struct pci_epc_features keembay_pcie_epc_features = {
 	.msi_capable		= true,
 	.msix_capable		= true,
 	.bar[BAR_0]		= { .only_64bit = true, },
-	.bar[BAR_1]		= { .type = BAR_RESERVED, },
+	.bar[BAR_1]		= { .type = BAR_64BIT_UPPER, },
 	.bar[BAR_2]		= { .only_64bit = true, },
-	.bar[BAR_3]		= { .type = BAR_RESERVED, },
+	.bar[BAR_3]		= { .type = BAR_64BIT_UPPER, },
 	.bar[BAR_4]		= { .only_64bit = true, },
-	.bar[BAR_5]		= { .type = BAR_RESERVED, },
+	.bar[BAR_5]		= { .type = BAR_64BIT_UPPER, },
 	.align			= SZ_16K,
 };
 
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index 18460f01b2c6..e55675b3840a 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -850,9 +850,9 @@ static const struct pci_epc_features qcom_pcie_epc_features = {
 	.msi_capable = true,
 	.align = SZ_4K,
 	.bar[BAR_0] = { .only_64bit = true, },
-	.bar[BAR_1] = { .type = BAR_RESERVED, },
+	.bar[BAR_1] = { .type = BAR_64BIT_UPPER, },
 	.bar[BAR_2] = { .only_64bit = true, },
-	.bar[BAR_3] = { .type = BAR_RESERVED, },
+	.bar[BAR_3] = { .type = BAR_64BIT_UPPER, },
 };
 
 static const struct pci_epc_features *
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 06571d806ab3..31aa9a494dbc 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1993,7 +1993,7 @@ static const struct pci_epc_features tegra_pcie_epc_features = {
 	.msi_capable = true,
 	.bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M,
 			.only_64bit = true, },
-	.bar[BAR_1] = { .type = BAR_RESERVED, },
+	.bar[BAR_1] = { .type = BAR_64BIT_UPPER, },
 	.bar[BAR_2] = { .type = BAR_RESERVED, },
 	.bar[BAR_3] = { .type = BAR_RESERVED, },
 	.bar[BAR_4] = { .type = BAR_RESERVED, },
diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
index d52753060970..f873a1659592 100644
--- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c
+++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
@@ -426,9 +426,9 @@ static const struct uniphier_pcie_ep_soc_data uniphier_pro5_data = {
 		.msix_capable = false,
 		.align = 1 << 16,
 		.bar[BAR_0] = { .only_64bit = true, },
-		.bar[BAR_1] = { .type = BAR_RESERVED, },
+		.bar[BAR_1] = { .type = BAR_64BIT_UPPER, },
 		.bar[BAR_2] = { .only_64bit = true, },
-		.bar[BAR_3] = { .type = BAR_RESERVED, },
+		.bar[BAR_3] = { .type = BAR_64BIT_UPPER, },
 		.bar[BAR_4] = { .type = BAR_RESERVED, },
 		.bar[BAR_5] = { .type = BAR_RESERVED, },
 	},
@@ -445,11 +445,11 @@ static const struct uniphier_pcie_ep_soc_data uniphier_nx1_data = {
 		.msix_capable = false,
 		.align = 1 << 12,
 		.bar[BAR_0] = { .only_64bit = true, },
-		.bar[BAR_1] = { .type = BAR_RESERVED, },
+		.bar[BAR_1] = { .type = BAR_64BIT_UPPER, },
 		.bar[BAR_2] = { .only_64bit = true, },
-		.bar[BAR_3] = { .type = BAR_RESERVED, },
+		.bar[BAR_3] = { .type = BAR_64BIT_UPPER, },
 		.bar[BAR_4] = { .only_64bit = true, },
-		.bar[BAR_5] = { .type = BAR_RESERVED, },
+		.bar[BAR_5] = { .type = BAR_64BIT_UPPER, },
 	},
 };
 
diff --git a/drivers/pci/controller/pcie-rcar-ep.c b/drivers/pci/controller/pcie-rcar-ep.c
index 657875ef4657..9b3f5391fabe 100644
--- a/drivers/pci/controller/pcie-rcar-ep.c
+++ b/drivers/pci/controller/pcie-rcar-ep.c
@@ -440,13 +440,13 @@ static const struct pci_epc_features rcar_pcie_epc_features = {
 	/* use 64-bit BARs so mark BAR[1,3,5] as reserved */
 	.bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = 128,
 			.only_64bit = true, },
-	.bar[BAR_1] = { .type = BAR_RESERVED, },
+	.bar[BAR_1] = { .type = BAR_64BIT_UPPER, },
 	.bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = 256,
 			.only_64bit = true, },
-	.bar[BAR_3] = { .type = BAR_RESERVED, },
+	.bar[BAR_3] = { .type = BAR_64BIT_UPPER, },
 	.bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = 256,
 			.only_64bit = true, },
-	.bar[BAR_5] = { .type = BAR_RESERVED, },
+	.bar[BAR_5] = { .type = BAR_64BIT_UPPER, },
 };
 
 static const struct pci_epc_features*
diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c
index 068155819c57..8de321e1c342 100644
--- a/drivers/pci/endpoint/pci-epc-core.c
+++ b/drivers/pci/endpoint/pci-epc-core.c
@@ -104,7 +104,8 @@ enum pci_barno pci_epc_get_next_free_bar(const struct pci_epc_features
 
 	for (i = bar; i < PCI_STD_NUM_BARS; i++) {
 		/* If the BAR is not reserved, return it. */
-		if (epc_features->bar[i].type != BAR_RESERVED)
+		if (epc_features->bar[i].type != BAR_RESERVED &&
+		    epc_features->bar[i].type != BAR_64BIT_UPPER)
 			return i;
 	}
 
diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
index c021c7af175f..c22f8a6cf9a3 100644
--- a/include/linux/pci-epc.h
+++ b/include/linux/pci-epc.h
@@ -192,12 +192,15 @@ struct pci_epc {
  *		   NOTE: An EPC driver can currently only set a single supported
  *		   size.
  * @BAR_RESERVED: The BAR should not be touched by an EPF driver.
+ * @BAR_64BIT_UPPER: Should only be set on a BAR if the preceding BAR is marked
+ *		     as only_64bit.
  */
 enum pci_epc_bar_type {
 	BAR_PROGRAMMABLE = 0,
 	BAR_FIXED,
 	BAR_RESIZABLE,
 	BAR_RESERVED,
+	BAR_64BIT_UPPER,
 };
 
 /**
@@ -207,7 +210,7 @@ enum pci_epc_bar_type {
  * @only_64bit: if true, an EPF driver is not allowed to choose if this BAR
  *		should be configured as 32-bit or 64-bit, the EPF driver must
  *		configure this BAR as 64-bit. Additionally, the BAR succeeding
- *		this BAR must be set to type BAR_RESERVED.
+ *		this BAR must be set to type BAR_64BIT_UPPER.
  *
  *		only_64bit should not be set on a BAR of type BAR_RESERVED.
  *		(If BARx is a 64-bit BAR that an EPF driver is not allowed to
-- 
2.53.0

Re: [PATCH 1/9] PCI: endpoint: Introduce pci_epc_bar_type BAR_64BIT_UPPER

[Frank Li]

On Tue, Feb 17, 2026 at 10:27:07PM +0100, Niklas Cassel wrote:
> Add a pci_epc_bar_type BAR_64BIT_UPPER to more clearly differentiate
> BAR_64BIT_UPPER from BAR_RESERVED.
>
> This BAR type will only be used for a BAR following a "only_64bit" BAR.
>
> This makes the BAR description more clear, and the reader does no longer
> need to check the BAR type for the preceding BAR to know how to interpret
> the BAR type.
>
> No functional changes.
>
> Signed-off-by: Niklas Cassel <cassel@kernel.org>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

>  drivers/pci/controller/dwc/pci-layerscape-ep.c |  4 ++--
>  drivers/pci/controller/dwc/pcie-keembay.c      |  6 +++---
>  drivers/pci/controller/dwc/pcie-qcom-ep.c      |  4 ++--
>  drivers/pci/controller/dwc/pcie-tegra194.c     |  2 +-
>  drivers/pci/controller/dwc/pcie-uniphier-ep.c  | 10 +++++-----
>  drivers/pci/controller/pcie-rcar-ep.c          |  6 +++---
>  drivers/pci/endpoint/pci-epc-core.c            |  3 ++-
>  include/linux/pci-epc.h                        |  5 ++++-
>  8 files changed, 22 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> index a4a800699f89..5a03a8f895f9 100644
> --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
> +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> @@ -251,9 +251,9 @@ static int __init ls_pcie_ep_probe(struct platform_device *pdev)
>  	pci->ops = pcie->drvdata->dw_pcie_ops;
>
>  	ls_epc->bar[BAR_2].only_64bit = true;
> -	ls_epc->bar[BAR_3].type = BAR_RESERVED;
> +	ls_epc->bar[BAR_3].type = BAR_64BIT_UPPER;
>  	ls_epc->bar[BAR_4].only_64bit = true;
> -	ls_epc->bar[BAR_5].type = BAR_RESERVED;
> +	ls_epc->bar[BAR_5].type = BAR_64BIT_UPPER;
>  	ls_epc->linkup_notifier = true;
>
>  	pcie->pci = pci;
> diff --git a/drivers/pci/controller/dwc/pcie-keembay.c b/drivers/pci/controller/dwc/pcie-keembay.c
> index 2666a9c3d67e..5a00b8cf5b53 100644
> --- a/drivers/pci/controller/dwc/pcie-keembay.c
> +++ b/drivers/pci/controller/dwc/pcie-keembay.c
> @@ -313,11 +313,11 @@ static const struct pci_epc_features keembay_pcie_epc_features = {
>  	.msi_capable		= true,
>  	.msix_capable		= true,
>  	.bar[BAR_0]		= { .only_64bit = true, },
> -	.bar[BAR_1]		= { .type = BAR_RESERVED, },
> +	.bar[BAR_1]		= { .type = BAR_64BIT_UPPER, },
>  	.bar[BAR_2]		= { .only_64bit = true, },
> -	.bar[BAR_3]		= { .type = BAR_RESERVED, },
> +	.bar[BAR_3]		= { .type = BAR_64BIT_UPPER, },
>  	.bar[BAR_4]		= { .only_64bit = true, },
> -	.bar[BAR_5]		= { .type = BAR_RESERVED, },
> +	.bar[BAR_5]		= { .type = BAR_64BIT_UPPER, },
>  	.align			= SZ_16K,
>  };
>
> diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> index 18460f01b2c6..e55675b3840a 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> @@ -850,9 +850,9 @@ static const struct pci_epc_features qcom_pcie_epc_features = {
>  	.msi_capable = true,
>  	.align = SZ_4K,
>  	.bar[BAR_0] = { .only_64bit = true, },
> -	.bar[BAR_1] = { .type = BAR_RESERVED, },
> +	.bar[BAR_1] = { .type = BAR_64BIT_UPPER, },
>  	.bar[BAR_2] = { .only_64bit = true, },
> -	.bar[BAR_3] = { .type = BAR_RESERVED, },
> +	.bar[BAR_3] = { .type = BAR_64BIT_UPPER, },
>  };
>
>  static const struct pci_epc_features *
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 06571d806ab3..31aa9a494dbc 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -1993,7 +1993,7 @@ static const struct pci_epc_features tegra_pcie_epc_features = {
>  	.msi_capable = true,
>  	.bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M,
>  			.only_64bit = true, },
> -	.bar[BAR_1] = { .type = BAR_RESERVED, },
> +	.bar[BAR_1] = { .type = BAR_64BIT_UPPER, },
>  	.bar[BAR_2] = { .type = BAR_RESERVED, },
>  	.bar[BAR_3] = { .type = BAR_RESERVED, },
>  	.bar[BAR_4] = { .type = BAR_RESERVED, },
> diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
> index d52753060970..f873a1659592 100644
> --- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
> @@ -426,9 +426,9 @@ static const struct uniphier_pcie_ep_soc_data uniphier_pro5_data = {
>  		.msix_capable = false,
>  		.align = 1 << 16,
>  		.bar[BAR_0] = { .only_64bit = true, },
> -		.bar[BAR_1] = { .type = BAR_RESERVED, },
> +		.bar[BAR_1] = { .type = BAR_64BIT_UPPER, },
>  		.bar[BAR_2] = { .only_64bit = true, },
> -		.bar[BAR_3] = { .type = BAR_RESERVED, },
> +		.bar[BAR_3] = { .type = BAR_64BIT_UPPER, },
>  		.bar[BAR_4] = { .type = BAR_RESERVED, },
>  		.bar[BAR_5] = { .type = BAR_RESERVED, },
>  	},
> @@ -445,11 +445,11 @@ static const struct uniphier_pcie_ep_soc_data uniphier_nx1_data = {
>  		.msix_capable = false,
>  		.align = 1 << 12,
>  		.bar[BAR_0] = { .only_64bit = true, },
> -		.bar[BAR_1] = { .type = BAR_RESERVED, },
> +		.bar[BAR_1] = { .type = BAR_64BIT_UPPER, },
>  		.bar[BAR_2] = { .only_64bit = true, },
> -		.bar[BAR_3] = { .type = BAR_RESERVED, },
> +		.bar[BAR_3] = { .type = BAR_64BIT_UPPER, },
>  		.bar[BAR_4] = { .only_64bit = true, },
> -		.bar[BAR_5] = { .type = BAR_RESERVED, },
> +		.bar[BAR_5] = { .type = BAR_64BIT_UPPER, },
>  	},
>  };
>
> diff --git a/drivers/pci/controller/pcie-rcar-ep.c b/drivers/pci/controller/pcie-rcar-ep.c
> index 657875ef4657..9b3f5391fabe 100644
> --- a/drivers/pci/controller/pcie-rcar-ep.c
> +++ b/drivers/pci/controller/pcie-rcar-ep.c
> @@ -440,13 +440,13 @@ static const struct pci_epc_features rcar_pcie_epc_features = {
>  	/* use 64-bit BARs so mark BAR[1,3,5] as reserved */
>  	.bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = 128,
>  			.only_64bit = true, },
> -	.bar[BAR_1] = { .type = BAR_RESERVED, },
> +	.bar[BAR_1] = { .type = BAR_64BIT_UPPER, },
>  	.bar[BAR_2] = { .type = BAR_FIXED, .fixed_size = 256,
>  			.only_64bit = true, },
> -	.bar[BAR_3] = { .type = BAR_RESERVED, },
> +	.bar[BAR_3] = { .type = BAR_64BIT_UPPER, },
>  	.bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = 256,
>  			.only_64bit = true, },
> -	.bar[BAR_5] = { .type = BAR_RESERVED, },
> +	.bar[BAR_5] = { .type = BAR_64BIT_UPPER, },
>  };
>
>  static const struct pci_epc_features*
> diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c
> index 068155819c57..8de321e1c342 100644
> --- a/drivers/pci/endpoint/pci-epc-core.c
> +++ b/drivers/pci/endpoint/pci-epc-core.c
> @@ -104,7 +104,8 @@ enum pci_barno pci_epc_get_next_free_bar(const struct pci_epc_features
>
>  	for (i = bar; i < PCI_STD_NUM_BARS; i++) {
>  		/* If the BAR is not reserved, return it. */
> -		if (epc_features->bar[i].type != BAR_RESERVED)
> +		if (epc_features->bar[i].type != BAR_RESERVED &&
> +		    epc_features->bar[i].type != BAR_64BIT_UPPER)
>  			return i;
>  	}
>
> diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
> index c021c7af175f..c22f8a6cf9a3 100644
> --- a/include/linux/pci-epc.h
> +++ b/include/linux/pci-epc.h
> @@ -192,12 +192,15 @@ struct pci_epc {
>   *		   NOTE: An EPC driver can currently only set a single supported
>   *		   size.
>   * @BAR_RESERVED: The BAR should not be touched by an EPF driver.
> + * @BAR_64BIT_UPPER: Should only be set on a BAR if the preceding BAR is marked
> + *		     as only_64bit.
>   */
>  enum pci_epc_bar_type {
>  	BAR_PROGRAMMABLE = 0,
>  	BAR_FIXED,
>  	BAR_RESIZABLE,
>  	BAR_RESERVED,
> +	BAR_64BIT_UPPER,
>  };
>
>  /**
> @@ -207,7 +210,7 @@ enum pci_epc_bar_type {
>   * @only_64bit: if true, an EPF driver is not allowed to choose if this BAR
>   *		should be configured as 32-bit or 64-bit, the EPF driver must
>   *		configure this BAR as 64-bit. Additionally, the BAR succeeding
> - *		this BAR must be set to type BAR_RESERVED.
> + *		this BAR must be set to type BAR_64BIT_UPPER.
>   *
>   *		only_64bit should not be set on a BAR of type BAR_RESERVED.
>   *		(If BARx is a 64-bit BAR that an EPF driver is not allowed to
> --
> 2.53.0
>

Re: [PATCH 1/9] PCI: endpoint: Introduce pci_epc_bar_type BAR_64BIT_UPPER

[Geert Uytterhoeven]

Hi Manikanta,

On Mon, 23 Feb 2026 at 04:57, Manikanta Maddireddy
<mmaddireddy@nvidia.com> wrote:
> On 18/02/26 3:27 am, Frank Li wrote:
>
> On Tue, Feb 17, 2026 at 10:27:07PM +0100, Niklas Cassel wrote:
>
> Add a pci_epc_bar_type BAR_64BIT_UPPER to more clearly differentiate
> BAR_64BIT_UPPER from BAR_RESERVED.
>
> This BAR type will only be used for a BAR following a "only_64bit" BAR.
>
> This makes the BAR description more clear, and the reader does no longer
> need to check the BAR type for the preceding BAR to know how to interpret
> the BAR type.
>
> No functional changes.
>
> Signed-off-by: Niklas Cassel <cassel@kernel.org>
> ---
>
> Reviewed-by: Frank Li <Frank.Li@nxp.com>
>
> Tested by: Manikanta Maddireddy <mmaddireddy@nvidia.com>

[...]

Please do not send HTML emails to the list, as they are rejected.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 1/9] PCI: endpoint: Introduce pci_epc_bar_type BAR_64BIT_UPPER

[Manikanta Maddireddy]

On 23/02/26 3:44 pm, Geert Uytterhoeven wrote:
> Hi Manikanta,
> 
> On Mon, 23 Feb 2026 at 04:57, Manikanta Maddireddy
> <mmaddireddy@nvidia.com> wrote:
>> On 18/02/26 3:27 am, Frank Li wrote:
>>
>> On Tue, Feb 17, 2026 at 10:27:07PM +0100, Niklas Cassel wrote:
>>
>> Add a pci_epc_bar_type BAR_64BIT_UPPER to more clearly differentiate
>> BAR_64BIT_UPPER from BAR_RESERVED.
>>
>> This BAR type will only be used for a BAR following a "only_64bit" BAR.
>>
>> This makes the BAR description more clear, and the reader does no longer
>> need to check the BAR type for the preceding BAR to know how to interpret
>> the BAR type.
>>
>> No functional changes.
>>
>> Signed-off-by: Niklas Cassel <cassel@kernel.org>
>> ---
>>
>> Reviewed-by: Frank Li <Frank.Li@nxp.com>
>>
>> Tested by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> 
> [...]
> 
> Please do not send HTML emails to the list, as they are rejected.
> 
> Gr{oetje,eeting}s,
> 
>                          Geert
> 

Apologies, I failed to realize that compose as html is checked in
my thunderbird client. I fixed it now.

Thanks,
Manikanta

-- 
nvpublic

[PATCH 2/9] PCI: endpoint: Describe reserved subregions within BARs

[Niklas Cassel]

From: Koichiro Den <den@valinux.co.jp>

Some endpoint controllers expose platform-owned, fixed register windows
within a BAR that EPF drivers must not reprogram (e.g. a BAR marked
BAR_RESERVED). Even in that case, EPF drivers may need to reference a
well-defined subset of that BAR, e.g. to reuse an integrated DMA
controller MMIO window as a doorbell target.

Introduce struct pci_epc_bar_rsvd_region and extend struct
pci_epc_bar_desc so EPC drivers can advertise such fixed subregions in a
controller-agnostic way.

No functional change for existing users.

Signed-off-by: Koichiro Den <den@valinux.co.jp>
Signed-off-by: Niklas Cassel <cassel@kernel.org>
---
 include/linux/pci-epc.h | 28 ++++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
index c22f8a6cf9a3..f7f48f43d370 100644
--- a/include/linux/pci-epc.h
+++ b/include/linux/pci-epc.h
@@ -203,6 +203,30 @@ enum pci_epc_bar_type {
 	BAR_64BIT_UPPER,
 };
 
+/**
+ * enum pci_epc_bar_rsvd_region_type - type of a fixed subregion behind a BAR
+ * @PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO: Integrated DMA controller MMIO window
+ *
+ * BARs marked BAR_RESERVED are owned by the SoC/EPC hardware and must not be
+ * reprogrammed by EPF drivers. Some of them still expose fixed subregions that
+ * EPFs may want to reference (e.g. embedded doorbell fallback).
+ */
+enum pci_epc_bar_rsvd_region_type {
+	PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO = 0,
+};
+
+/**
+ * struct pci_epc_bar_rsvd_region - fixed subregion behind a BAR
+ * @type: reserved region type
+ * @offset: offset within the BAR aperture
+ * @size: size of the reserved region
+ */
+struct pci_epc_bar_rsvd_region {
+	enum pci_epc_bar_rsvd_region_type	type;
+	resource_size_t				offset;
+	resource_size_t				size;
+};
+
 /**
  * struct pci_epc_bar_desc - hardware description for a BAR
  * @type: the type of the BAR
@@ -216,11 +240,15 @@ enum pci_epc_bar_type {
  *		(If BARx is a 64-bit BAR that an EPF driver is not allowed to
  *		touch, then both BARx and BARx+1 must be set to type
  *		BAR_RESERVED.)
+ * @nr_rsvd_regions: number of fixed subregions described for BAR_RESERVED
+ * @rsvd_regions: fixed subregions behind BAR_RESERVED
  */
 struct pci_epc_bar_desc {
 	enum pci_epc_bar_type type;
 	u64 fixed_size;
 	bool only_64bit;
+	u8 nr_rsvd_regions;
+	const struct pci_epc_bar_rsvd_region *rsvd_regions;
 };
 
 /**
-- 
2.53.0

Re: [PATCH 2/9] PCI: endpoint: Describe reserved subregions within BARs

[Manikanta Maddireddy]

On 18/02/26 2:57 am, Niklas Cassel wrote:
> From: Koichiro Den <den@valinux.co.jp>
>
> Some endpoint controllers expose platform-owned, fixed register windows
> within a BAR that EPF drivers must not reprogram (e.g. a BAR marked
> BAR_RESERVED). Even in that case, EPF drivers may need to reference a
> well-defined subset of that BAR, e.g. to reuse an integrated DMA
> controller MMIO window as a doorbell target.
>
> Introduce struct pci_epc_bar_rsvd_region and extend struct
> pci_epc_bar_desc so EPC drivers can advertise such fixed subregions in a
> controller-agnostic way.
>
> No functional change for existing users.
>
> Signed-off-by: Koichiro Den <den@valinux.co.jp>
> Signed-off-by: Niklas Cassel <cassel@kernel.org>
Tested by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> ---
>   include/linux/pci-epc.h | 28 ++++++++++++++++++++++++++++
>   1 file changed, 28 insertions(+)
>
> diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
> index c22f8a6cf9a3..f7f48f43d370 100644
> --- a/include/linux/pci-epc.h
> +++ b/include/linux/pci-epc.h
> @@ -203,6 +203,30 @@ enum pci_epc_bar_type {
>   	BAR_64BIT_UPPER,
>   };
>   
> +/**
> + * enum pci_epc_bar_rsvd_region_type - type of a fixed subregion behind a BAR
> + * @PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO: Integrated DMA controller MMIO window
> + *
> + * BARs marked BAR_RESERVED are owned by the SoC/EPC hardware and must not be
> + * reprogrammed by EPF drivers. Some of them still expose fixed subregions that
> + * EPFs may want to reference (e.g. embedded doorbell fallback).
> + */
> +enum pci_epc_bar_rsvd_region_type {
> +	PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO = 0,
> +};
> +
> +/**
> + * struct pci_epc_bar_rsvd_region - fixed subregion behind a BAR
> + * @type: reserved region type
> + * @offset: offset within the BAR aperture
> + * @size: size of the reserved region
> + */
> +struct pci_epc_bar_rsvd_region {
> +	enum pci_epc_bar_rsvd_region_type	type;
> +	resource_size_t				offset;
> +	resource_size_t				size;
> +};
> +
>   /**
>    * struct pci_epc_bar_desc - hardware description for a BAR
>    * @type: the type of the BAR
> @@ -216,11 +240,15 @@ enum pci_epc_bar_type {
>    *		(If BARx is a 64-bit BAR that an EPF driver is not allowed to
>    *		touch, then both BARx and BARx+1 must be set to type
>    *		BAR_RESERVED.)
> + * @nr_rsvd_regions: number of fixed subregions described for BAR_RESERVED
> + * @rsvd_regions: fixed subregions behind BAR_RESERVED
>    */
>   struct pci_epc_bar_desc {
>   	enum pci_epc_bar_type type;
>   	u64 fixed_size;
>   	bool only_64bit;
> +	u8 nr_rsvd_regions;
> +	const struct pci_epc_bar_rsvd_region *rsvd_regions;
>   };
>   
>   /**

[PATCH 3/9] PCI: dw-rockchip: Describe RK3588 BAR4 DMA ctrl window

[Niklas Cassel]

From: Koichiro Den <den@valinux.co.jp>

On RK3588 PCIe3_4L in EP mode, the integrated DMA controller registers
are permanently mapped to BAR4 and must not be repurposed by EPF
drivers.

When the remote peer needs to access these registers, it must use the
fixed BAR4 window instead of creating another inbound mapping in a
different BAR. Mixing the fixed window with an additional mapping can
lead to incorrect behavior.

Advertise the DMA controller MMIO window as a reserved BAR subregion so
EPF drivers can reuse it safely.

Signed-off-by: Koichiro Den <den@valinux.co.jp>
Signed-off-by: Niklas Cassel <cassel@kernel.org>
---
 drivers/pci/controller/dwc/pcie-dw-rockchip.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index 5b17da63151d..ecc28093c589 100644
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -403,6 +403,15 @@ static const struct pci_epc_features rockchip_pcie_epc_features_rk3568 = {
 	.bar[BAR_5] = { .type = BAR_RESIZABLE, },
 };
 
+static const struct pci_epc_bar_rsvd_region rk3588_bar4_rsvd[] = {
+	{
+		/* DMA_CAP (BAR4: DMA Port Logic Structure) */
+		.type = PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO,
+		.offset = 0x0,
+		.size = 0x2000,
+	},
+};
+
 /*
  * BAR4 on rk3588 exposes the ATU Port Logic Structure to the host regardless of
  * iATU settings for BAR4. This means that BAR4 cannot be used by an EPF driver,
@@ -420,7 +429,11 @@ static const struct pci_epc_features rockchip_pcie_epc_features_rk3588 = {
 	.bar[BAR_1] = { .type = BAR_RESIZABLE, },
 	.bar[BAR_2] = { .type = BAR_RESIZABLE, },
 	.bar[BAR_3] = { .type = BAR_RESIZABLE, },
-	.bar[BAR_4] = { .type = BAR_RESERVED, },
+	.bar[BAR_4] = {
+		.type = BAR_RESERVED,
+		.nr_rsvd_regions = ARRAY_SIZE(rk3588_bar4_rsvd),
+		.rsvd_regions = rk3588_bar4_rsvd,
+	},
 	.bar[BAR_5] = { .type = BAR_RESIZABLE, },
 };
 
-- 
2.53.0

Re: [PATCH 3/9] PCI: dw-rockchip: Describe RK3588 BAR4 DMA ctrl window

[Manikanta Maddireddy]

On 18/02/26 2:57 am, Niklas Cassel wrote:
> From: Koichiro Den <den@valinux.co.jp>
>
> On RK3588 PCIe3_4L in EP mode, the integrated DMA controller registers
> are permanently mapped to BAR4 and must not be repurposed by EPF
> drivers.
>
> When the remote peer needs to access these registers, it must use the
> fixed BAR4 window instead of creating another inbound mapping in a
> different BAR. Mixing the fixed window with an additional mapping can
> lead to incorrect behavior.
>
> Advertise the DMA controller MMIO window as a reserved BAR subregion so
> EPF drivers can reuse it safely.
>
> Signed-off-by: Koichiro Den <den@valinux.co.jp>
> Signed-off-by: Niklas Cassel <cassel@kernel.org>
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
I have not verified this on rk3588, therefore I am not adding "Tested 
by" tag
> ---
>   drivers/pci/controller/dwc/pcie-dw-rockchip.c | 15 ++++++++++++++-
>   1 file changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> index 5b17da63151d..ecc28093c589 100644
> --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> @@ -403,6 +403,15 @@ static const struct pci_epc_features rockchip_pcie_epc_features_rk3568 = {
>   	.bar[BAR_5] = { .type = BAR_RESIZABLE, },
>   };
>   
> +static const struct pci_epc_bar_rsvd_region rk3588_bar4_rsvd[] = {
> +	{
> +		/* DMA_CAP (BAR4: DMA Port Logic Structure) */
> +		.type = PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO,
> +		.offset = 0x0,
> +		.size = 0x2000,
> +	},
> +};
> +
>   /*
>    * BAR4 on rk3588 exposes the ATU Port Logic Structure to the host regardless of
>    * iATU settings for BAR4. This means that BAR4 cannot be used by an EPF driver,
> @@ -420,7 +429,11 @@ static const struct pci_epc_features rockchip_pcie_epc_features_rk3588 = {
>   	.bar[BAR_1] = { .type = BAR_RESIZABLE, },
>   	.bar[BAR_2] = { .type = BAR_RESIZABLE, },
>   	.bar[BAR_3] = { .type = BAR_RESIZABLE, },
> -	.bar[BAR_4] = { .type = BAR_RESERVED, },
> +	.bar[BAR_4] = {
> +		.type = BAR_RESERVED,
> +		.nr_rsvd_regions = ARRAY_SIZE(rk3588_bar4_rsvd),
> +		.rsvd_regions = rk3588_bar4_rsvd,
> +	},
>   	.bar[BAR_5] = { .type = BAR_RESIZABLE, },
>   };
>   

[PATCH 4/9] PCI: endpoint: Introduce pci_epc_bar_type BAR_DISABLED

[Niklas Cassel]

Add a pci_epc_bar_type BAR_64BIT_UPPER to more clearly differentiate
BAR_DISABLED from BAR_RESERVED.

This BAR type will only be used for a BAR that the EPC driver should
disable. (Unlike a BAR_RESERVED, which is still enabled.)

Co-developed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Signed-off-by: Niklas Cassel <cassel@kernel.org>
---
 drivers/pci/endpoint/pci-epc-core.c |  5 +++--
 include/linux/pci-epc.h             | 12 ++++++++++--
 2 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c
index 8de321e1c342..5045e22367cf 100644
--- a/drivers/pci/endpoint/pci-epc-core.c
+++ b/drivers/pci/endpoint/pci-epc-core.c
@@ -103,9 +103,10 @@ enum pci_barno pci_epc_get_next_free_bar(const struct pci_epc_features
 		bar++;
 
 	for (i = bar; i < PCI_STD_NUM_BARS; i++) {
-		/* If the BAR is not reserved, return it. */
+		/* If the BAR is not reserved or disabled, return it. */
 		if (epc_features->bar[i].type != BAR_RESERVED &&
-		    epc_features->bar[i].type != BAR_64BIT_UPPER)
+		    epc_features->bar[i].type != BAR_64BIT_UPPER &&
+		    epc_features->bar[i].type != BAR_DISABLED)
 			return i;
 	}
 
diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
index f7f48f43d370..8687b9c3462b 100644
--- a/include/linux/pci-epc.h
+++ b/include/linux/pci-epc.h
@@ -191,7 +191,14 @@ struct pci_epc {
  * @BAR_RESIZABLE: The BAR implements the PCI-SIG Resizable BAR Capability.
  *		   NOTE: An EPC driver can currently only set a single supported
  *		   size.
- * @BAR_RESERVED: The BAR should not be touched by an EPF driver.
+ * @BAR_RESERVED: Used for HW-backed BARs (e.g. MSI-X table, DMA regs). The BAR
+ *		  should not be disabled an EPC driver. The BAR should not be
+ *		  reprogrammed by an EPF driver. An EPF driver is allowed to
+ *		  disable the BAR if absolutely necessary. (However, right now
+ *		  there is no EPC operation to disable a BAR that has not been
+ *		  programmed using pci_epc_set_bar().)
+ * @BAR_DISABLED: The BAR should be disabled by an EPC driver. The BAR will be
+ *		  unavailable to an EPF driver.
  * @BAR_64BIT_UPPER: Should only be set on a BAR if the preceding BAR is marked
  *		     as only_64bit.
  */
@@ -200,6 +207,7 @@ enum pci_epc_bar_type {
 	BAR_FIXED,
 	BAR_RESIZABLE,
 	BAR_RESERVED,
+	BAR_DISABLED,
 	BAR_64BIT_UPPER,
 };
 
@@ -238,7 +246,7 @@ struct pci_epc_bar_rsvd_region {
  *
  *		only_64bit should not be set on a BAR of type BAR_RESERVED.
  *		(If BARx is a 64-bit BAR that an EPF driver is not allowed to
- *		touch, then both BARx and BARx+1 must be set to type
+ *		reprogram, then both BARx and BARx+1 must be set to type
  *		BAR_RESERVED.)
  * @nr_rsvd_regions: number of fixed subregions described for BAR_RESERVED
  * @rsvd_regions: fixed subregions behind BAR_RESERVED
-- 
2.53.0

Re: [PATCH 4/9] PCI: endpoint: Introduce pci_epc_bar_type BAR_DISABLED

[Frank Li]

On Tue, Feb 17, 2026 at 10:27:10PM +0100, Niklas Cassel wrote:
> Add a pci_epc_bar_type BAR_64BIT_UPPER to more clearly differentiate

s/BAR_64BIT_UPPER/BAR_DISABLED/

> BAR_DISABLED from BAR_RESERVED.

from BAR_RESERVED.

>
> This BAR type will only be used for a BAR that the EPC driver should
> disable. (Unlike a BAR_RESERVED, which is still enabled.)

confused. it looks, "this bar type will be never used by EPC drivers"

Frank

>
> Co-developed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> Signed-off-by: Niklas Cassel <cassel@kernel.org>
> ---
>  drivers/pci/endpoint/pci-epc-core.c |  5 +++--
>  include/linux/pci-epc.h             | 12 ++++++++++--
>  2 files changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c
> index 8de321e1c342..5045e22367cf 100644
> --- a/drivers/pci/endpoint/pci-epc-core.c
> +++ b/drivers/pci/endpoint/pci-epc-core.c
> @@ -103,9 +103,10 @@ enum pci_barno pci_epc_get_next_free_bar(const struct pci_epc_features
>  		bar++;
>
>  	for (i = bar; i < PCI_STD_NUM_BARS; i++) {
> -		/* If the BAR is not reserved, return it. */
> +		/* If the BAR is not reserved or disabled, return it. */
>  		if (epc_features->bar[i].type != BAR_RESERVED &&
> -		    epc_features->bar[i].type != BAR_64BIT_UPPER)
> +		    epc_features->bar[i].type != BAR_64BIT_UPPER &&
> +		    epc_features->bar[i].type != BAR_DISABLED)
>  			return i;
>  	}
>
> diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
> index f7f48f43d370..8687b9c3462b 100644
> --- a/include/linux/pci-epc.h
> +++ b/include/linux/pci-epc.h
> @@ -191,7 +191,14 @@ struct pci_epc {
>   * @BAR_RESIZABLE: The BAR implements the PCI-SIG Resizable BAR Capability.
>   *		   NOTE: An EPC driver can currently only set a single supported
>   *		   size.
> - * @BAR_RESERVED: The BAR should not be touched by an EPF driver.
> + * @BAR_RESERVED: Used for HW-backed BARs (e.g. MSI-X table, DMA regs). The BAR
> + *		  should not be disabled an EPC driver. The BAR should not be
> + *		  reprogrammed by an EPF driver. An EPF driver is allowed to
> + *		  disable the BAR if absolutely necessary. (However, right now
> + *		  there is no EPC operation to disable a BAR that has not been
> + *		  programmed using pci_epc_set_bar().)
> + * @BAR_DISABLED: The BAR should be disabled by an EPC driver. The BAR will be
> + *		  unavailable to an EPF driver.
>   * @BAR_64BIT_UPPER: Should only be set on a BAR if the preceding BAR is marked
>   *		     as only_64bit.
>   */
> @@ -200,6 +207,7 @@ enum pci_epc_bar_type {
>  	BAR_FIXED,
>  	BAR_RESIZABLE,
>  	BAR_RESERVED,
> +	BAR_DISABLED,
>  	BAR_64BIT_UPPER,
>  };
>
> @@ -238,7 +246,7 @@ struct pci_epc_bar_rsvd_region {
>   *
>   *		only_64bit should not be set on a BAR of type BAR_RESERVED.
>   *		(If BARx is a 64-bit BAR that an EPF driver is not allowed to
> - *		touch, then both BARx and BARx+1 must be set to type
> + *		reprogram, then both BARx and BARx+1 must be set to type
>   *		BAR_RESERVED.)
>   * @nr_rsvd_regions: number of fixed subregions described for BAR_RESERVED
>   * @rsvd_regions: fixed subregions behind BAR_RESERVED
> --
> 2.53.0
>

Re: [PATCH 4/9] PCI: endpoint: Introduce pci_epc_bar_type BAR_DISABLED

[Niklas Cassel]

On Tue, Feb 17, 2026 at 05:03:29PM -0500, Frank Li wrote:
> On Tue, Feb 17, 2026 at 10:27:10PM +0100, Niklas Cassel wrote:
> > Add a pci_epc_bar_type BAR_64BIT_UPPER to more clearly differentiate
> 
> s/BAR_64BIT_UPPER/BAR_DISABLED/
> 
> > BAR_DISABLED from BAR_RESERVED.
> 
> from BAR_RESERVED.
> 
> >
> > This BAR type will only be used for a BAR that the EPC driver should
> > disable. (Unlike a BAR_RESERVED, which is still enabled.)
> 
> confused. it looks, "this bar type will be never used by EPC drivers"

I could write it as:
"This BAR type will only be used to describe a BAR that the EPC driver
should disable, and will thus never be available to an EPF drive.
(Unlike BAR_RESERVED, which will never by be disabled by default by an
EPC driver.)"

Is that more clear?


Kind regards,
Niklas

Re: [PATCH 4/9] PCI: endpoint: Introduce pci_epc_bar_type BAR_DISABLED

[Frank Li]

On Wed, Feb 18, 2026 at 11:33:39AM +0100, Niklas Cassel wrote:
> On Tue, Feb 17, 2026 at 05:03:29PM -0500, Frank Li wrote:
> > On Tue, Feb 17, 2026 at 10:27:10PM +0100, Niklas Cassel wrote:
> > > Add a pci_epc_bar_type BAR_64BIT_UPPER to more clearly differentiate
> >
> > s/BAR_64BIT_UPPER/BAR_DISABLED/
> >
> > > BAR_DISABLED from BAR_RESERVED.
> >
> > from BAR_RESERVED.
> >
> > >
> > > This BAR type will only be used for a BAR that the EPC driver should
> > > disable. (Unlike a BAR_RESERVED, which is still enabled.)
> >
> > confused. it looks, "this bar type will be never used by EPC drivers"
>
> I could write it as:
> "This BAR type will only be used to describe a BAR that the EPC driver
> should disable, and will thus never be available to an EPF drive.
> (Unlike BAR_RESERVED, which will never by be disabled by default by an
> EPC driver.)"
>
> Is that more clear?

Yes, jsut remove "by" between "never" and "be"

Frank

>
>
> Kind regards,
> Niklas

Re: [PATCH 4/9] PCI: endpoint: Introduce pci_epc_bar_type BAR_DISABLED

[Manikanta Maddireddy]

On 18/02/26 3:33 am, Frank Li wrote:
> On Tue, Feb 17, 2026 at 10:27:10PM +0100, Niklas Cassel wrote:
>> Add a pci_epc_bar_type BAR_64BIT_UPPER to more clearly differentiate
> s/BAR_64BIT_UPPER/BAR_DISABLED/
>
>> BAR_DISABLED from BAR_RESERVED.
> from BAR_RESERVED.
>
>> This BAR type will only be used for a BAR that the EPC driver should
>> disable. (Unlike a BAR_RESERVED, which is still enabled.)
> confused. it looks, "this bar type will be never used by EPC drivers"
>
> Frank
>
>> Co-developed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>> Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>> Signed-off-by: Niklas Cassel <cassel@kernel.org>
Tested by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
with the comment fixes
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>> ---
>>   drivers/pci/endpoint/pci-epc-core.c |  5 +++--
>>   include/linux/pci-epc.h             | 12 ++++++++++--
>>   2 files changed, 13 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c
>> index 8de321e1c342..5045e22367cf 100644
>> --- a/drivers/pci/endpoint/pci-epc-core.c
>> +++ b/drivers/pci/endpoint/pci-epc-core.c
>> @@ -103,9 +103,10 @@ enum pci_barno pci_epc_get_next_free_bar(const struct pci_epc_features
>>   		bar++;
>>
>>   	for (i = bar; i < PCI_STD_NUM_BARS; i++) {
>> -		/* If the BAR is not reserved, return it. */
>> +		/* If the BAR is not reserved or disabled, return it. */
>>   		if (epc_features->bar[i].type != BAR_RESERVED &&
>> -		    epc_features->bar[i].type != BAR_64BIT_UPPER)
>> +		    epc_features->bar[i].type != BAR_64BIT_UPPER &&
>> +		    epc_features->bar[i].type != BAR_DISABLED)
>>   			return i;
>>   	}
>>
>> diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h
>> index f7f48f43d370..8687b9c3462b 100644
>> --- a/include/linux/pci-epc.h
>> +++ b/include/linux/pci-epc.h
>> @@ -191,7 +191,14 @@ struct pci_epc {
>>    * @BAR_RESIZABLE: The BAR implements the PCI-SIG Resizable BAR Capability.
>>    *		   NOTE: An EPC driver can currently only set a single supported
>>    *		   size.
>> - * @BAR_RESERVED: The BAR should not be touched by an EPF driver.
>> + * @BAR_RESERVED: Used for HW-backed BARs (e.g. MSI-X table, DMA regs). The BAR
>> + *		  should not be disabled an EPC driver. The BAR should not be

should not be disabled by an EPC driver. The BAR should not be
>> + *		  reprogrammed by an EPF driver. An EPF driver is allowed to
>> + *		  disable the BAR if absolutely necessary. (However, right now
>> + *		  there is no EPC operation to disable a BAR that has not been
>> + *		  programmed using pci_epc_set_bar().)
>> + * @BAR_DISABLED: The BAR should be disabled by an EPC driver. The BAR will be
>> + *		  unavailable to an EPF driver.
>>    * @BAR_64BIT_UPPER: Should only be set on a BAR if the preceding BAR is marked
>>    *		     as only_64bit.
>>    */
>> @@ -200,6 +207,7 @@ enum pci_epc_bar_type {
>>   	BAR_FIXED,
>>   	BAR_RESIZABLE,
>>   	BAR_RESERVED,
>> +	BAR_DISABLED,
>>   	BAR_64BIT_UPPER,
>>   };
>>
>> @@ -238,7 +246,7 @@ struct pci_epc_bar_rsvd_region {
>>    *
>>    *		only_64bit should not be set on a BAR of type BAR_RESERVED.
>>    *		(If BARx is a 64-bit BAR that an EPF driver is not allowed to
>> - *		touch, then both BARx and BARx+1 must be set to type
>> + *		reprogram, then both BARx and BARx+1 must be set to type
>>    *		BAR_RESERVED.)
>>    * @nr_rsvd_regions: number of fixed subregions described for BAR_RESERVED
>>    * @rsvd_regions: fixed subregions behind BAR_RESERVED
>> --
>> 2.53.0
>>

[PATCH 5/9] PCI: dwc: Replace BAR_RESERVED with BAR_DISABLED in glue drivers

[Niklas Cassel]

Most DWC based EPC glue drivers that have BARs marked as BAR_RESERVED in
epc_features also call dw_pcie_ep_reset_bar() for these reserved BARs in
ep->ops->init().

An EPF driver will be able to get/enable BARs that have been disabled/reset
unless they are marked as BAR_RESERVED (see pci_epc_get_next_free_bar()).

Thus all EPC drivers that have a BAR marked as BAR_RESERVED in epc_features
AND call dw_pcie_ep_reset_bar() should really be marked as BAR_DISABLED.

BARs that are marked as BAR_RESERVED in epc_features but for which
dw_pcie_ep_reset_bar() is not called in ep->ops->init() are still kept as
BAR_RESERVED.

No EPC drivers outside drivers/pci/controllers/dwc mark their BARs as
BAR_RESERVED, so there is nothing to do in non-DWC based EPC drivers.

Signed-off-by: Niklas Cassel <cassel@kernel.org>
---
 drivers/pci/controller/dwc/pci-imx6.c         | 12 ++++++------
 drivers/pci/controller/dwc/pcie-rcar-gen4.c   |  6 +++---
 drivers/pci/controller/dwc/pcie-tegra194.c    |  8 ++++----
 drivers/pci/controller/dwc/pcie-uniphier-ep.c |  4 ++--
 4 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index a5b8d0b71677..ec1e3557ca53 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -1433,19 +1433,19 @@ static int imx_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
 static const struct pci_epc_features imx8m_pcie_epc_features = {
 	DWC_EPC_COMMON_FEATURES,
 	.msi_capable = true,
-	.bar[BAR_1] = { .type = BAR_RESERVED, },
-	.bar[BAR_3] = { .type = BAR_RESERVED, },
+	.bar[BAR_1] = { .type = BAR_DISABLED, },
+	.bar[BAR_3] = { .type = BAR_DISABLED, },
 	.bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = SZ_256, },
-	.bar[BAR_5] = { .type = BAR_RESERVED, },
+	.bar[BAR_5] = { .type = BAR_DISABLED, },
 	.align = SZ_64K,
 };
 
 static const struct pci_epc_features imx8q_pcie_epc_features = {
 	DWC_EPC_COMMON_FEATURES,
 	.msi_capable = true,
-	.bar[BAR_1] = { .type = BAR_RESERVED, },
-	.bar[BAR_3] = { .type = BAR_RESERVED, },
-	.bar[BAR_5] = { .type = BAR_RESERVED, },
+	.bar[BAR_1] = { .type = BAR_DISABLED, },
+	.bar[BAR_3] = { .type = BAR_DISABLED, },
+	.bar[BAR_5] = { .type = BAR_DISABLED, },
 	.align = SZ_64K,
 };
 
diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
index a6912e85e4dd..9dd05bac22b9 100644
--- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c
+++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
@@ -422,10 +422,10 @@ static int rcar_gen4_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
 static const struct pci_epc_features rcar_gen4_pcie_epc_features = {
 	DWC_EPC_COMMON_FEATURES,
 	.msi_capable = true,
-	.bar[BAR_1] = { .type = BAR_RESERVED, },
-	.bar[BAR_3] = { .type = BAR_RESERVED, },
+	.bar[BAR_1] = { .type = BAR_DISABLED, },
+	.bar[BAR_3] = { .type = BAR_DISABLED, },
 	.bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = 256 },
-	.bar[BAR_5] = { .type = BAR_RESERVED, },
+	.bar[BAR_5] = { .type = BAR_DISABLED, },
 	.align = SZ_1M,
 };
 
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 31aa9a494dbc..9f9453e8cd23 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1994,10 +1994,10 @@ static const struct pci_epc_features tegra_pcie_epc_features = {
 	.bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M,
 			.only_64bit = true, },
 	.bar[BAR_1] = { .type = BAR_64BIT_UPPER, },
-	.bar[BAR_2] = { .type = BAR_RESERVED, },
-	.bar[BAR_3] = { .type = BAR_RESERVED, },
-	.bar[BAR_4] = { .type = BAR_RESERVED, },
-	.bar[BAR_5] = { .type = BAR_RESERVED, },
+	.bar[BAR_2] = { .type = BAR_DISABLED, },
+	.bar[BAR_3] = { .type = BAR_DISABLED, },
+	.bar[BAR_4] = { .type = BAR_DISABLED, },
+	.bar[BAR_5] = { .type = BAR_DISABLED, },
 	.align = SZ_64K,
 };
 
diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
index f873a1659592..5bde3ee682b5 100644
--- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c
+++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
@@ -429,8 +429,8 @@ static const struct uniphier_pcie_ep_soc_data uniphier_pro5_data = {
 		.bar[BAR_1] = { .type = BAR_64BIT_UPPER, },
 		.bar[BAR_2] = { .only_64bit = true, },
 		.bar[BAR_3] = { .type = BAR_64BIT_UPPER, },
-		.bar[BAR_4] = { .type = BAR_RESERVED, },
-		.bar[BAR_5] = { .type = BAR_RESERVED, },
+		.bar[BAR_4] = { .type = BAR_DISABLED, },
+		.bar[BAR_5] = { .type = BAR_DISABLED, },
 	},
 };
 
-- 
2.53.0

Re: [PATCH 5/9] PCI: dwc: Replace BAR_RESERVED with BAR_DISABLED in glue drivers

[Frank Li]

On Tue, Feb 17, 2026 at 10:27:11PM +0100, Niklas Cassel wrote:
> Most DWC based EPC glue drivers that have BARs marked as BAR_RESERVED in
> epc_features also call dw_pcie_ep_reset_bar() for these reserved BARs in
> ep->ops->init().
>
> An EPF driver will be able to get/enable BARs that have been disabled/reset
> unless they are marked as BAR_RESERVED (see pci_epc_get_next_free_bar()).
>
> Thus all EPC drivers that have a BAR marked as BAR_RESERVED in epc_features
> AND call dw_pcie_ep_reset_bar() should really be marked as BAR_DISABLED.
>
> BARs that are marked as BAR_RESERVED in epc_features but for which
> dw_pcie_ep_reset_bar() is not called in ep->ops->init() are still kept as
> BAR_RESERVED.

combine the same condition together to make easy to read. like

"For BAR_RESERVED bars, change to BAR_DISABLED if call dw_pcie_ep_reset_bar().
and keep as BAR_RESERVED if not dw_pcie_ep_reset_bar() in ep-ops-init()"

Frank

>
> No EPC drivers outside drivers/pci/controllers/dwc mark their BARs as
> BAR_RESERVED, so there is nothing to do in non-DWC based EPC drivers.
>
> Signed-off-by: Niklas Cassel <cassel@kernel.org>
> ---
>  drivers/pci/controller/dwc/pci-imx6.c         | 12 ++++++------
>  drivers/pci/controller/dwc/pcie-rcar-gen4.c   |  6 +++---
>  drivers/pci/controller/dwc/pcie-tegra194.c    |  8 ++++----
>  drivers/pci/controller/dwc/pcie-uniphier-ep.c |  4 ++--
>  4 files changed, 15 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index a5b8d0b71677..ec1e3557ca53 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -1433,19 +1433,19 @@ static int imx_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>  static const struct pci_epc_features imx8m_pcie_epc_features = {
>  	DWC_EPC_COMMON_FEATURES,
>  	.msi_capable = true,
> -	.bar[BAR_1] = { .type = BAR_RESERVED, },
> -	.bar[BAR_3] = { .type = BAR_RESERVED, },
> +	.bar[BAR_1] = { .type = BAR_DISABLED, },
> +	.bar[BAR_3] = { .type = BAR_DISABLED, },
>  	.bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = SZ_256, },
> -	.bar[BAR_5] = { .type = BAR_RESERVED, },
> +	.bar[BAR_5] = { .type = BAR_DISABLED, },
>  	.align = SZ_64K,
>  };
>
>  static const struct pci_epc_features imx8q_pcie_epc_features = {
>  	DWC_EPC_COMMON_FEATURES,
>  	.msi_capable = true,
> -	.bar[BAR_1] = { .type = BAR_RESERVED, },
> -	.bar[BAR_3] = { .type = BAR_RESERVED, },
> -	.bar[BAR_5] = { .type = BAR_RESERVED, },
> +	.bar[BAR_1] = { .type = BAR_DISABLED, },
> +	.bar[BAR_3] = { .type = BAR_DISABLED, },
> +	.bar[BAR_5] = { .type = BAR_DISABLED, },
>  	.align = SZ_64K,
>  };
>
> diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> index a6912e85e4dd..9dd05bac22b9 100644
> --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> @@ -422,10 +422,10 @@ static int rcar_gen4_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>  static const struct pci_epc_features rcar_gen4_pcie_epc_features = {
>  	DWC_EPC_COMMON_FEATURES,
>  	.msi_capable = true,
> -	.bar[BAR_1] = { .type = BAR_RESERVED, },
> -	.bar[BAR_3] = { .type = BAR_RESERVED, },
> +	.bar[BAR_1] = { .type = BAR_DISABLED, },
> +	.bar[BAR_3] = { .type = BAR_DISABLED, },
>  	.bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = 256 },
> -	.bar[BAR_5] = { .type = BAR_RESERVED, },
> +	.bar[BAR_5] = { .type = BAR_DISABLED, },
>  	.align = SZ_1M,
>  };
>
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 31aa9a494dbc..9f9453e8cd23 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -1994,10 +1994,10 @@ static const struct pci_epc_features tegra_pcie_epc_features = {
>  	.bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M,
>  			.only_64bit = true, },
>  	.bar[BAR_1] = { .type = BAR_64BIT_UPPER, },
> -	.bar[BAR_2] = { .type = BAR_RESERVED, },
> -	.bar[BAR_3] = { .type = BAR_RESERVED, },
> -	.bar[BAR_4] = { .type = BAR_RESERVED, },
> -	.bar[BAR_5] = { .type = BAR_RESERVED, },
> +	.bar[BAR_2] = { .type = BAR_DISABLED, },
> +	.bar[BAR_3] = { .type = BAR_DISABLED, },
> +	.bar[BAR_4] = { .type = BAR_DISABLED, },
> +	.bar[BAR_5] = { .type = BAR_DISABLED, },
>  	.align = SZ_64K,
>  };
>
> diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
> index f873a1659592..5bde3ee682b5 100644
> --- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
> @@ -429,8 +429,8 @@ static const struct uniphier_pcie_ep_soc_data uniphier_pro5_data = {
>  		.bar[BAR_1] = { .type = BAR_64BIT_UPPER, },
>  		.bar[BAR_2] = { .only_64bit = true, },
>  		.bar[BAR_3] = { .type = BAR_64BIT_UPPER, },
> -		.bar[BAR_4] = { .type = BAR_RESERVED, },
> -		.bar[BAR_5] = { .type = BAR_RESERVED, },
> +		.bar[BAR_4] = { .type = BAR_DISABLED, },
> +		.bar[BAR_5] = { .type = BAR_DISABLED, },
>  	},
>  };
>
> --
> 2.53.0
>

Re: [PATCH 5/9] PCI: dwc: Replace BAR_RESERVED with BAR_DISABLED in glue drivers

[Manikanta Maddireddy]

On 18/02/26 3:45 am, Frank Li wrote:
> On Tue, Feb 17, 2026 at 10:27:11PM +0100, Niklas Cassel wrote:
>> Most DWC based EPC glue drivers that have BARs marked as BAR_RESERVED in
>> epc_features also call dw_pcie_ep_reset_bar() for these reserved BARs in
>> ep->ops->init().
>>
>> An EPF driver will be able to get/enable BARs that have been disabled/reset
>> unless they are marked as BAR_RESERVED (see pci_epc_get_next_free_bar()).
>>
>> Thus all EPC drivers that have a BAR marked as BAR_RESERVED in epc_features
>> AND call dw_pcie_ep_reset_bar() should really be marked as BAR_DISABLED.
>>
>> BARs that are marked as BAR_RESERVED in epc_features but for which
>> dw_pcie_ep_reset_bar() is not called in ep->ops->init() are still kept as
>> BAR_RESERVED.
> combine the same condition together to make easy to read. like
>
> "For BAR_RESERVED bars, change to BAR_DISABLED if call dw_pcie_ep_reset_bar().
> and keep as BAR_RESERVED if not dw_pcie_ep_reset_bar() in ep-ops-init()"
>
> Frank
>
>> No EPC drivers outside drivers/pci/controllers/dwc mark their BARs as
>> BAR_RESERVED, so there is nothing to do in non-DWC based EPC drivers.
>>
>> Signed-off-by: Niklas Cassel <cassel@kernel.org>
Tested by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>> ---
>>   drivers/pci/controller/dwc/pci-imx6.c         | 12 ++++++------
>>   drivers/pci/controller/dwc/pcie-rcar-gen4.c   |  6 +++---
>>   drivers/pci/controller/dwc/pcie-tegra194.c    |  8 ++++----
>>   drivers/pci/controller/dwc/pcie-uniphier-ep.c |  4 ++--
I see BAR_RESERVED in pci-keystone.c driver in linux-next branch.
Do you have any patch which changed BAR_RESERVED to different type
in pci-keystone.c driver?
>>   4 files changed, 15 insertions(+), 15 deletions(-)
>>
>> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
>> index a5b8d0b71677..ec1e3557ca53 100644
>> --- a/drivers/pci/controller/dwc/pci-imx6.c
>> +++ b/drivers/pci/controller/dwc/pci-imx6.c
>> @@ -1433,19 +1433,19 @@ static int imx_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>>   static const struct pci_epc_features imx8m_pcie_epc_features = {
>>   	DWC_EPC_COMMON_FEATURES,
>>   	.msi_capable = true,
>> -	.bar[BAR_1] = { .type = BAR_RESERVED, },
>> -	.bar[BAR_3] = { .type = BAR_RESERVED, },
>> +	.bar[BAR_1] = { .type = BAR_DISABLED, },
>> +	.bar[BAR_3] = { .type = BAR_DISABLED, },
>>   	.bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = SZ_256, },
>> -	.bar[BAR_5] = { .type = BAR_RESERVED, },
>> +	.bar[BAR_5] = { .type = BAR_DISABLED, },
>>   	.align = SZ_64K,
>>   };
>>
>>   static const struct pci_epc_features imx8q_pcie_epc_features = {
>>   	DWC_EPC_COMMON_FEATURES,
>>   	.msi_capable = true,
>> -	.bar[BAR_1] = { .type = BAR_RESERVED, },
>> -	.bar[BAR_3] = { .type = BAR_RESERVED, },
>> -	.bar[BAR_5] = { .type = BAR_RESERVED, },
>> +	.bar[BAR_1] = { .type = BAR_DISABLED, },
>> +	.bar[BAR_3] = { .type = BAR_DISABLED, },
>> +	.bar[BAR_5] = { .type = BAR_DISABLED, },
>>   	.align = SZ_64K,
>>   };
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
>> index a6912e85e4dd..9dd05bac22b9 100644
>> --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c
>> +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
>> @@ -422,10 +422,10 @@ static int rcar_gen4_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>>   static const struct pci_epc_features rcar_gen4_pcie_epc_features = {
>>   	DWC_EPC_COMMON_FEATURES,
>>   	.msi_capable = true,
>> -	.bar[BAR_1] = { .type = BAR_RESERVED, },
>> -	.bar[BAR_3] = { .type = BAR_RESERVED, },
>> +	.bar[BAR_1] = { .type = BAR_DISABLED, },
>> +	.bar[BAR_3] = { .type = BAR_DISABLED, },
>>   	.bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = 256 },
>> -	.bar[BAR_5] = { .type = BAR_RESERVED, },
>> +	.bar[BAR_5] = { .type = BAR_DISABLED, },
>>   	.align = SZ_1M,
>>   };
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
>> index 31aa9a494dbc..9f9453e8cd23 100644
>> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
>> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
>> @@ -1994,10 +1994,10 @@ static const struct pci_epc_features tegra_pcie_epc_features = {
>>   	.bar[BAR_0] = { .type = BAR_FIXED, .fixed_size = SZ_1M,
>>   			.only_64bit = true, },
>>   	.bar[BAR_1] = { .type = BAR_64BIT_UPPER, },
>> -	.bar[BAR_2] = { .type = BAR_RESERVED, },
>> -	.bar[BAR_3] = { .type = BAR_RESERVED, },
>> -	.bar[BAR_4] = { .type = BAR_RESERVED, },
>> -	.bar[BAR_5] = { .type = BAR_RESERVED, },
>> +	.bar[BAR_2] = { .type = BAR_DISABLED, },
>> +	.bar[BAR_3] = { .type = BAR_DISABLED, },
>> +	.bar[BAR_4] = { .type = BAR_DISABLED, },
>> +	.bar[BAR_5] = { .type = BAR_DISABLED, },
>>   	.align = SZ_64K,
>>   };
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
>> index f873a1659592..5bde3ee682b5 100644
>> --- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c
>> +++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
>> @@ -429,8 +429,8 @@ static const struct uniphier_pcie_ep_soc_data uniphier_pro5_data = {
>>   		.bar[BAR_1] = { .type = BAR_64BIT_UPPER, },
>>   		.bar[BAR_2] = { .only_64bit = true, },
>>   		.bar[BAR_3] = { .type = BAR_64BIT_UPPER, },
>> -		.bar[BAR_4] = { .type = BAR_RESERVED, },
>> -		.bar[BAR_5] = { .type = BAR_RESERVED, },
>> +		.bar[BAR_4] = { .type = BAR_DISABLED, },
>> +		.bar[BAR_5] = { .type = BAR_DISABLED, },
>>   	},
>>   };
>>
>> --
>> 2.53.0
>>

Re: [PATCH 5/9] PCI: dwc: Replace BAR_RESERVED with BAR_DISABLED in glue drivers

[Niklas Cassel]

On Mon, Feb 23, 2026 at 10:16:51AM +0530, Manikanta Maddireddy wrote:
> 
> On 18/02/26 3:45 am, Frank Li wrote:
> > On Tue, Feb 17, 2026 at 10:27:11PM +0100, Niklas Cassel wrote:
> > > Most DWC based EPC glue drivers that have BARs marked as BAR_RESERVED in
> > > epc_features also call dw_pcie_ep_reset_bar() for these reserved BARs in
> > > ep->ops->init().
> > > 
> > > An EPF driver will be able to get/enable BARs that have been disabled/reset
> > > unless they are marked as BAR_RESERVED (see pci_epc_get_next_free_bar()).
> > > 
> > > Thus all EPC drivers that have a BAR marked as BAR_RESERVED in epc_features
> > > AND call dw_pcie_ep_reset_bar() should really be marked as BAR_DISABLED.
> > > 
> > > BARs that are marked as BAR_RESERVED in epc_features but for which
> > > dw_pcie_ep_reset_bar() is not called in ep->ops->init() are still kept as
> > > BAR_RESERVED.
> > combine the same condition together to make easy to read. like
> > 
> > "For BAR_RESERVED bars, change to BAR_DISABLED if call dw_pcie_ep_reset_bar().
> > and keep as BAR_RESERVED if not dw_pcie_ep_reset_bar() in ep-ops-init()"
> > 
> > Frank
> > 
> > > No EPC drivers outside drivers/pci/controllers/dwc mark their BARs as
> > > BAR_RESERVED, so there is nothing to do in non-DWC based EPC drivers.
> > > 
> > > Signed-off-by: Niklas Cassel <cassel@kernel.org>

Note: the proper tag is Tested-by.
(I noticed that b4 did not pick up your tags.)

> Tested by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> > > ---
> > >   drivers/pci/controller/dwc/pci-imx6.c         | 12 ++++++------
> > >   drivers/pci/controller/dwc/pcie-rcar-gen4.c   |  6 +++---
> > >   drivers/pci/controller/dwc/pcie-tegra194.c    |  8 ++++----
> > >   drivers/pci/controller/dwc/pcie-uniphier-ep.c |  4 ++--

> I see BAR_RESERVED in pci-keystone.c driver in linux-next branch.
> Do you have any patch which changed BAR_RESERVED to different type
> in pci-keystone.c driver?

No, I did not change keystone, because that is the only DWC base glue driver
that has never disabled these BARs by default.

I will add a TODO to the keystone driver:

diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
index 20fa4dadb82a..576a78a9f6e5 100644
--- a/drivers/pci/controller/dwc/pci-keystone.c
+++ b/drivers/pci/controller/dwc/pci-keystone.c
@@ -933,6 +933,11 @@ static const struct pci_epc_features ks_pcie_am654_epc_features = {
        DWC_EPC_COMMON_FEATURES,
        .msi_capable = true,
        .msix_capable = true,
+       /*
+        * TODO: BAR_RESERVED should either be replaced with BAR_DISABLED or,
+        * if the should continue to be enabled, then the driver should define
+        * what is behind the reserved BARs, see struct pci_epc_bar_rsvd_region.
+        */
        .bar[BAR_0] = { .type = BAR_RESERVED, },
        .bar[BAR_1] = { .type = BAR_RESERVED, },
        .bar[BAR_2] = { .type = BAR_RESIZABLE, },

[PATCH 6/9] PCI: dwc: Disable BARs in common code instead of in each glue driver

[Niklas Cassel]

The current EPC core design relies on an EPC driver disabling all BARs by
default. An EPF driver will then enable the BARs that it wants to enabled.

This design is there because there is no epc->ops->disable_bar().
(There is a epc->ops->clear_bar(), but that is only to disable a BAR that
has been enabled using epc->ops->set_bar() first.)

By default, an EPF driver will not be able to get/enable BARs that are
marked as BAR_RESERVED or BAR_DISABLED (see pci_epc_get_next_free_bar()).

Since the current EPC code design requires an EPC driver to disable all
BARs by default, let's do this in the DWC common code rather than in each
glue driver.

BARs that are marked as BAR_RESERVED are not disabled by default.
This is because these BARs are hardware backed, and should only be disabled
explicitly by an EPF driver if absolutely necessary for the EPF driver to
function correctly. (This is similar to how e.g. NVMe may have vendor
specific BARs outside of the mandatory BAR0 which contains the NVMe
registers.)

Note that there is currently no EPC operation to disable a BAR that has not
first been programmed using pci_epc_set_bar(). If an EPF driver ever wants
to disable a BAR marked as BAR_RESERVED, a disable_bar() operation would
have to be added first.

No functional changes intended.

Signed-off-by: Niklas Cassel <cassel@kernel.org>
---
 drivers/pci/controller/dwc/pci-dra7xx.c       |  4 ----
 drivers/pci/controller/dwc/pci-imx6.c         | 10 --------
 .../pci/controller/dwc/pci-layerscape-ep.c    |  4 ----
 drivers/pci/controller/dwc/pcie-artpec6.c     |  4 ----
 .../pci/controller/dwc/pcie-designware-ep.c   | 24 +++++++++++++++++++
 .../pci/controller/dwc/pcie-designware-plat.c | 10 --------
 drivers/pci/controller/dwc/pcie-dw-rockchip.c |  4 ----
 drivers/pci/controller/dwc/pcie-qcom-ep.c     | 10 --------
 drivers/pci/controller/dwc/pcie-rcar-gen4.c   | 10 --------
 drivers/pci/controller/dwc/pcie-stm32-ep.c    | 10 --------
 drivers/pci/controller/dwc/pcie-tegra194.c    | 10 --------
 drivers/pci/controller/dwc/pcie-uniphier-ep.c | 10 --------
 12 files changed, 24 insertions(+), 86 deletions(-)

diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
index d5d26229063f..cd904659c321 100644
--- a/drivers/pci/controller/dwc/pci-dra7xx.c
+++ b/drivers/pci/controller/dwc/pci-dra7xx.c
@@ -378,10 +378,6 @@ static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
 	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
-	enum pci_barno bar;
-
-	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
-		dw_pcie_ep_reset_bar(pci, bar);
 
 	dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
 }
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index ec1e3557ca53..f5fe5cfc46c7 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -1401,15 +1401,6 @@ static const struct dw_pcie_ops dw_pcie_ops = {
 	.stop_link = imx_pcie_stop_link,
 };
 
-static void imx_pcie_ep_init(struct dw_pcie_ep *ep)
-{
-	enum pci_barno bar;
-	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
-
-	for (bar = BAR_0; bar <= BAR_5; bar++)
-		dw_pcie_ep_reset_bar(pci, bar);
-}
-
 static int imx_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
 				  unsigned int type, u16 interrupt_num)
 {
@@ -1478,7 +1469,6 @@ imx_pcie_ep_get_features(struct dw_pcie_ep *ep)
 }
 
 static const struct dw_pcie_ep_ops pcie_ep_ops = {
-	.init = imx_pcie_ep_init,
 	.raise_irq = imx_pcie_ep_raise_irq,
 	.get_features = imx_pcie_ep_get_features,
 };
diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
index 5a03a8f895f9..1f5fccdb4ff4 100644
--- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
+++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
@@ -152,15 +152,11 @@ static void ls_pcie_ep_init(struct dw_pcie_ep *ep)
 	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
 	struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);
 	struct dw_pcie_ep_func *ep_func;
-	enum pci_barno bar;
 
 	ep_func = dw_pcie_ep_get_func_from_ep(ep, 0);
 	if (!ep_func)
 		return;
 
-	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
-		dw_pcie_ep_reset_bar(pci, bar);
-
 	pcie->ls_epc->msi_capable = ep_func->msi_cap ? true : false;
 	pcie->ls_epc->msix_capable = ep_func->msix_cap ? true : false;
 }
diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c
index e994b75986c3..55cb957ae1f3 100644
--- a/drivers/pci/controller/dwc/pcie-artpec6.c
+++ b/drivers/pci/controller/dwc/pcie-artpec6.c
@@ -340,15 +340,11 @@ static void artpec6_pcie_ep_init(struct dw_pcie_ep *ep)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
 	struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
-	enum pci_barno bar;
 
 	artpec6_pcie_assert_core_reset(artpec6_pcie);
 	artpec6_pcie_init_phy(artpec6_pcie);
 	artpec6_pcie_deassert_core_reset(artpec6_pcie);
 	artpec6_pcie_wait_for_phy(artpec6_pcie);
-
-	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
-		dw_pcie_ep_reset_bar(pci, bar);
 }
 
 static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 7e7844ff0f7e..5e47517c757c 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -1105,6 +1105,28 @@ static void dw_pcie_ep_init_non_sticky_registers(struct dw_pcie *pci)
 	dw_pcie_dbi_ro_wr_dis(pci);
 }
 
+static void dw_pcie_ep_disable_bars(struct dw_pcie_ep *ep)
+{
+	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+	enum pci_epc_bar_type bar_type;
+	enum pci_barno bar;
+
+	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
+		bar_type = dw_pcie_ep_get_bar_type(ep, bar);
+
+		/*
+		 * Reserved BARs should not get disabled by default. All other
+		 * BAR types are disabled by default.
+		 *
+		 * This is in line with the current EPC core design, where all
+		 * BARs are disabled by default, and then the EPF driver enables
+		 * the BARs it wishes to use.
+		 */
+		if (bar_type != BAR_RESERVED)
+			dw_pcie_ep_reset_bar(pci, bar);
+	}
+}
+
 /**
  * dw_pcie_ep_init_registers - Initialize DWC EP specific registers
  * @ep: DWC EP device
@@ -1187,6 +1209,8 @@ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep)
 	if (ep->ops->init)
 		ep->ops->init(ep);
 
+	dw_pcie_ep_disable_bars(ep);
+
 	/*
 	 * PCIe r6.0, section 7.9.15 states that for endpoints that support
 	 * PTM, this capability structure is required in exactly one
diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c
index 8530746ec5cb..d103ab759c4e 100644
--- a/drivers/pci/controller/dwc/pcie-designware-plat.c
+++ b/drivers/pci/controller/dwc/pcie-designware-plat.c
@@ -32,15 +32,6 @@ struct dw_plat_pcie_of_data {
 static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = {
 };
 
-static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep)
-{
-	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
-	enum pci_barno bar;
-
-	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
-		dw_pcie_ep_reset_bar(pci, bar);
-}
-
 static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
 				     unsigned int type, u16 interrupt_num)
 {
@@ -73,7 +64,6 @@ dw_plat_pcie_get_features(struct dw_pcie_ep *ep)
 }
 
 static const struct dw_pcie_ep_ops pcie_ep_ops = {
-	.init = dw_plat_pcie_ep_init,
 	.raise_irq = dw_plat_pcie_ep_raise_irq,
 	.get_features = dw_plat_pcie_get_features,
 };
diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
index ecc28093c589..4e9b813c3afb 100644
--- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
+++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
@@ -361,13 +361,9 @@ static void rockchip_pcie_ep_hide_broken_ats_cap_rk3588(struct dw_pcie_ep *ep)
 static void rockchip_pcie_ep_init(struct dw_pcie_ep *ep)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
-	enum pci_barno bar;
 
 	rockchip_pcie_enable_l0s(pci);
 	rockchip_pcie_ep_hide_broken_ats_cap_rk3588(ep);
-
-	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
-		dw_pcie_ep_reset_bar(pci, bar);
 };
 
 static int rockchip_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
index e55675b3840a..e8c8ba1659fd 100644
--- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
+++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
@@ -861,17 +861,7 @@ qcom_pcie_epc_get_features(struct dw_pcie_ep *pci_ep)
 	return &qcom_pcie_epc_features;
 }
 
-static void qcom_pcie_ep_init(struct dw_pcie_ep *ep)
-{
-	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
-	enum pci_barno bar;
-
-	for (bar = BAR_0; bar <= BAR_5; bar++)
-		dw_pcie_ep_reset_bar(pci, bar);
-}
-
 static const struct dw_pcie_ep_ops pci_ep_ops = {
-	.init = qcom_pcie_ep_init,
 	.raise_irq = qcom_pcie_ep_raise_irq,
 	.get_features = qcom_pcie_epc_get_features,
 };
diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
index 9dd05bac22b9..1198ddc1752c 100644
--- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c
+++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
@@ -386,15 +386,6 @@ static void rcar_gen4_pcie_ep_pre_init(struct dw_pcie_ep *ep)
 	writel(PCIEDMAINTSTSEN_INIT, rcar->base + PCIEDMAINTSTSEN);
 }
 
-static void rcar_gen4_pcie_ep_init(struct dw_pcie_ep *ep)
-{
-	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
-	enum pci_barno bar;
-
-	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
-		dw_pcie_ep_reset_bar(pci, bar);
-}
-
 static void rcar_gen4_pcie_ep_deinit(struct rcar_gen4_pcie *rcar)
 {
 	writel(0, rcar->base + PCIEDMAINTSTSEN);
@@ -449,7 +440,6 @@ static unsigned int rcar_gen4_pcie_ep_get_dbi2_offset(struct dw_pcie_ep *ep,
 
 static const struct dw_pcie_ep_ops pcie_ep_ops = {
 	.pre_init = rcar_gen4_pcie_ep_pre_init,
-	.init = rcar_gen4_pcie_ep_init,
 	.raise_irq = rcar_gen4_pcie_ep_raise_irq,
 	.get_features = rcar_gen4_pcie_ep_get_features,
 	.get_dbi_offset = rcar_gen4_pcie_ep_get_dbi_offset,
diff --git a/drivers/pci/controller/dwc/pcie-stm32-ep.c b/drivers/pci/controller/dwc/pcie-stm32-ep.c
index c1944b40ce02..a7988dff1045 100644
--- a/drivers/pci/controller/dwc/pcie-stm32-ep.c
+++ b/drivers/pci/controller/dwc/pcie-stm32-ep.c
@@ -28,15 +28,6 @@ struct stm32_pcie {
 	unsigned int perst_irq;
 };
 
-static void stm32_pcie_ep_init(struct dw_pcie_ep *ep)
-{
-	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
-	enum pci_barno bar;
-
-	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
-		dw_pcie_ep_reset_bar(pci, bar);
-}
-
 static int stm32_pcie_start_link(struct dw_pcie *pci)
 {
 	struct stm32_pcie *stm32_pcie = to_stm32_pcie(pci);
@@ -82,7 +73,6 @@ stm32_pcie_get_features(struct dw_pcie_ep *ep)
 }
 
 static const struct dw_pcie_ep_ops stm32_pcie_ep_ops = {
-	.init = stm32_pcie_ep_init,
 	.raise_irq = stm32_pcie_raise_irq,
 	.get_features = stm32_pcie_get_features,
 };
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 9f9453e8cd23..3a6bffaff9ea 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1923,15 +1923,6 @@ static irqreturn_t tegra_pcie_ep_pex_rst_irq(int irq, void *arg)
 	return IRQ_HANDLED;
 }
 
-static void tegra_pcie_ep_init(struct dw_pcie_ep *ep)
-{
-	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
-	enum pci_barno bar;
-
-	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
-		dw_pcie_ep_reset_bar(pci, bar);
-};
-
 static int tegra_pcie_ep_raise_intx_irq(struct tegra_pcie_dw *pcie, u16 irq)
 {
 	/* Tegra194 supports only INTA */
@@ -2008,7 +1999,6 @@ tegra_pcie_ep_get_features(struct dw_pcie_ep *ep)
 }
 
 static const struct dw_pcie_ep_ops pcie_ep_ops = {
-	.init = tegra_pcie_ep_init,
 	.raise_irq = tegra_pcie_ep_raise_irq,
 	.get_features = tegra_pcie_ep_get_features,
 };
diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
index 5bde3ee682b5..494376d1812d 100644
--- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c
+++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
@@ -203,15 +203,6 @@ static void uniphier_pcie_stop_link(struct dw_pcie *pci)
 	uniphier_pcie_ltssm_enable(priv, false);
 }
 
-static void uniphier_pcie_ep_init(struct dw_pcie_ep *ep)
-{
-	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
-	enum pci_barno bar;
-
-	for (bar = BAR_0; bar <= BAR_5; bar++)
-		dw_pcie_ep_reset_bar(pci, bar);
-}
-
 static int uniphier_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
@@ -283,7 +274,6 @@ uniphier_pcie_get_features(struct dw_pcie_ep *ep)
 }
 
 static const struct dw_pcie_ep_ops uniphier_pcie_ep_ops = {
-	.init = uniphier_pcie_ep_init,
 	.raise_irq = uniphier_pcie_ep_raise_irq,
 	.get_features = uniphier_pcie_get_features,
 };
-- 
2.53.0

Re: [PATCH 6/9] PCI: dwc: Disable BARs in common code instead of in each glue driver

[Frank Li]

On Tue, Feb 17, 2026 at 10:27:12PM +0100, Niklas Cassel wrote:
> The current EPC core design relies on an EPC driver disabling all BARs by
> default. An EPF driver will then enable the BARs that it wants to enabled.
>
> This design is there because there is no epc->ops->disable_bar().
> (There is a epc->ops->clear_bar(), but that is only to disable a BAR that
> has been enabled using epc->ops->set_bar() first.)
>
> By default, an EPF driver will not be able to get/enable BARs that are
> marked as BAR_RESERVED or BAR_DISABLED (see pci_epc_get_next_free_bar()).
>
> Since the current EPC code design requires an EPC driver to disable all
> BARs by default, let's do this in the DWC common code rather than in each
> glue driver.

Move this to DWC common code from each glue driver.

>
> BARs that are marked as BAR_RESERVED are not disabled by default.
> This is because these BARs are hardware backed, and should only be disabled

Needn't "this is",  ... are not disabled by default because these BARS ..


> explicitly by an EPF driver if absolutely necessary for the EPF driver to
> function correctly. (This is similar to how e.g. NVMe may have vendor
> specific BARs outside of the mandatory BAR0 which contains the NVMe
> registers.)
>
> Note that there is currently no EPC operation to disable a BAR that has not
> first been programmed using pci_epc_set_bar(). If an EPF driver ever wants
> to disable a BAR marked as BAR_RESERVED, a disable_bar() operation would
> have to be added first.
>
> No functional changes intended.
>
> Signed-off-by: Niklas Cassel <cassel@kernel.org>
> ---
>  drivers/pci/controller/dwc/pci-dra7xx.c       |  4 ----
>  drivers/pci/controller/dwc/pci-imx6.c         | 10 --------
>  .../pci/controller/dwc/pci-layerscape-ep.c    |  4 ----
>  drivers/pci/controller/dwc/pcie-artpec6.c     |  4 ----
>  .../pci/controller/dwc/pcie-designware-ep.c   | 24 +++++++++++++++++++
>  .../pci/controller/dwc/pcie-designware-plat.c | 10 --------
>  drivers/pci/controller/dwc/pcie-dw-rockchip.c |  4 ----
>  drivers/pci/controller/dwc/pcie-qcom-ep.c     | 10 --------
>  drivers/pci/controller/dwc/pcie-rcar-gen4.c   | 10 --------
>  drivers/pci/controller/dwc/pcie-stm32-ep.c    | 10 --------
>  drivers/pci/controller/dwc/pcie-tegra194.c    | 10 --------
>  drivers/pci/controller/dwc/pcie-uniphier-ep.c | 10 --------
>  12 files changed, 24 insertions(+), 86 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-dra7xx.c b/drivers/pci/controller/dwc/pci-dra7xx.c
> index d5d26229063f..cd904659c321 100644
> --- a/drivers/pci/controller/dwc/pci-dra7xx.c
> +++ b/drivers/pci/controller/dwc/pci-dra7xx.c
> @@ -378,10 +378,6 @@ static void dra7xx_pcie_ep_init(struct dw_pcie_ep *ep)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>  	struct dra7xx_pcie *dra7xx = to_dra7xx_pcie(pci);
> -	enum pci_barno bar;
> -
> -	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
> -		dw_pcie_ep_reset_bar(pci, bar);
>
>  	dra7xx_pcie_enable_wrapper_interrupts(dra7xx);
>  }
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index ec1e3557ca53..f5fe5cfc46c7 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -1401,15 +1401,6 @@ static const struct dw_pcie_ops dw_pcie_ops = {
>  	.stop_link = imx_pcie_stop_link,
>  };
>
> -static void imx_pcie_ep_init(struct dw_pcie_ep *ep)
> -{
> -	enum pci_barno bar;
> -	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> -
> -	for (bar = BAR_0; bar <= BAR_5; bar++)
> -		dw_pcie_ep_reset_bar(pci, bar);
> -}
> -
>  static int imx_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>  				  unsigned int type, u16 interrupt_num)
>  {
> @@ -1478,7 +1469,6 @@ imx_pcie_ep_get_features(struct dw_pcie_ep *ep)
>  }
>
>  static const struct dw_pcie_ep_ops pcie_ep_ops = {
> -	.init = imx_pcie_ep_init,
>  	.raise_irq = imx_pcie_ep_raise_irq,
>  	.get_features = imx_pcie_ep_get_features,
>  };
> diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> index 5a03a8f895f9..1f5fccdb4ff4 100644
> --- a/drivers/pci/controller/dwc/pci-layerscape-ep.c
> +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> @@ -152,15 +152,11 @@ static void ls_pcie_ep_init(struct dw_pcie_ep *ep)
>  	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>  	struct ls_pcie_ep *pcie = to_ls_pcie_ep(pci);
>  	struct dw_pcie_ep_func *ep_func;
> -	enum pci_barno bar;
>
>  	ep_func = dw_pcie_ep_get_func_from_ep(ep, 0);
>  	if (!ep_func)
>  		return;
>
> -	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
> -		dw_pcie_ep_reset_bar(pci, bar);
> -
>  	pcie->ls_epc->msi_capable = ep_func->msi_cap ? true : false;
>  	pcie->ls_epc->msix_capable = ep_func->msix_cap ? true : false;
>  }
> diff --git a/drivers/pci/controller/dwc/pcie-artpec6.c b/drivers/pci/controller/dwc/pcie-artpec6.c
> index e994b75986c3..55cb957ae1f3 100644
> --- a/drivers/pci/controller/dwc/pcie-artpec6.c
> +++ b/drivers/pci/controller/dwc/pcie-artpec6.c
> @@ -340,15 +340,11 @@ static void artpec6_pcie_ep_init(struct dw_pcie_ep *ep)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
>  	struct artpec6_pcie *artpec6_pcie = to_artpec6_pcie(pci);
> -	enum pci_barno bar;
>
>  	artpec6_pcie_assert_core_reset(artpec6_pcie);
>  	artpec6_pcie_init_phy(artpec6_pcie);
>  	artpec6_pcie_deassert_core_reset(artpec6_pcie);
>  	artpec6_pcie_wait_for_phy(artpec6_pcie);
> -
> -	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
> -		dw_pcie_ep_reset_bar(pci, bar);
>  }
>
>  static int artpec6_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
> index 7e7844ff0f7e..5e47517c757c 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
> @@ -1105,6 +1105,28 @@ static void dw_pcie_ep_init_non_sticky_registers(struct dw_pcie *pci)
>  	dw_pcie_dbi_ro_wr_dis(pci);
>  }
>
> +static void dw_pcie_ep_disable_bars(struct dw_pcie_ep *ep)
> +{
> +	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> +	enum pci_epc_bar_type bar_type;
> +	enum pci_barno bar;
> +
> +	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
> +		bar_type = dw_pcie_ep_get_bar_type(ep, bar);
> +
> +		/*
> +		 * Reserved BARs should not get disabled by default. All other
> +		 * BAR types are disabled by default.
> +		 *
> +		 * This is in line with the current EPC core design, where all
> +		 * BARs are disabled by default, and then the EPF driver enables
> +		 * the BARs it wishes to use.
> +		 */
> +		if (bar_type != BAR_RESERVED)
> +			dw_pcie_ep_reset_bar(pci, bar);

Any bad impact if reset a RESERVED bar?

Frank

> +	}
> +}
> +
>  /**
>   * dw_pcie_ep_init_registers - Initialize DWC EP specific registers
>   * @ep: DWC EP device
> @@ -1187,6 +1209,8 @@ int dw_pcie_ep_init_registers(struct dw_pcie_ep *ep)
>  	if (ep->ops->init)
>  		ep->ops->init(ep);
>
> +	dw_pcie_ep_disable_bars(ep);
> +
>  	/*
>  	 * PCIe r6.0, section 7.9.15 states that for endpoints that support
>  	 * PTM, this capability structure is required in exactly one
> diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c
> index 8530746ec5cb..d103ab759c4e 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-plat.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c
> @@ -32,15 +32,6 @@ struct dw_plat_pcie_of_data {
>  static const struct dw_pcie_host_ops dw_plat_pcie_host_ops = {
>  };
>
> -static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep)
> -{
> -	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> -	enum pci_barno bar;
> -
> -	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
> -		dw_pcie_ep_reset_bar(pci, bar);
> -}
> -
>  static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
>  				     unsigned int type, u16 interrupt_num)
>  {
> @@ -73,7 +64,6 @@ dw_plat_pcie_get_features(struct dw_pcie_ep *ep)
>  }
>
>  static const struct dw_pcie_ep_ops pcie_ep_ops = {
> -	.init = dw_plat_pcie_ep_init,
>  	.raise_irq = dw_plat_pcie_ep_raise_irq,
>  	.get_features = dw_plat_pcie_get_features,
>  };
> diff --git a/drivers/pci/controller/dwc/pcie-dw-rockchip.c b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> index ecc28093c589..4e9b813c3afb 100644
> --- a/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> +++ b/drivers/pci/controller/dwc/pcie-dw-rockchip.c
> @@ -361,13 +361,9 @@ static void rockchip_pcie_ep_hide_broken_ats_cap_rk3588(struct dw_pcie_ep *ep)
>  static void rockchip_pcie_ep_init(struct dw_pcie_ep *ep)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> -	enum pci_barno bar;
>
>  	rockchip_pcie_enable_l0s(pci);
>  	rockchip_pcie_ep_hide_broken_ats_cap_rk3588(ep);
> -
> -	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
> -		dw_pcie_ep_reset_bar(pci, bar);
>  };
>
>  static int rockchip_pcie_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> index e55675b3840a..e8c8ba1659fd 100644
> --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c
> @@ -861,17 +861,7 @@ qcom_pcie_epc_get_features(struct dw_pcie_ep *pci_ep)
>  	return &qcom_pcie_epc_features;
>  }
>
> -static void qcom_pcie_ep_init(struct dw_pcie_ep *ep)
> -{
> -	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> -	enum pci_barno bar;
> -
> -	for (bar = BAR_0; bar <= BAR_5; bar++)
> -		dw_pcie_ep_reset_bar(pci, bar);
> -}
> -
>  static const struct dw_pcie_ep_ops pci_ep_ops = {
> -	.init = qcom_pcie_ep_init,
>  	.raise_irq = qcom_pcie_ep_raise_irq,
>  	.get_features = qcom_pcie_epc_get_features,
>  };
> diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4.c b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> index 9dd05bac22b9..1198ddc1752c 100644
> --- a/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4.c
> @@ -386,15 +386,6 @@ static void rcar_gen4_pcie_ep_pre_init(struct dw_pcie_ep *ep)
>  	writel(PCIEDMAINTSTSEN_INIT, rcar->base + PCIEDMAINTSTSEN);
>  }
>
> -static void rcar_gen4_pcie_ep_init(struct dw_pcie_ep *ep)
> -{
> -	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> -	enum pci_barno bar;
> -
> -	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
> -		dw_pcie_ep_reset_bar(pci, bar);
> -}
> -
>  static void rcar_gen4_pcie_ep_deinit(struct rcar_gen4_pcie *rcar)
>  {
>  	writel(0, rcar->base + PCIEDMAINTSTSEN);
> @@ -449,7 +440,6 @@ static unsigned int rcar_gen4_pcie_ep_get_dbi2_offset(struct dw_pcie_ep *ep,
>
>  static const struct dw_pcie_ep_ops pcie_ep_ops = {
>  	.pre_init = rcar_gen4_pcie_ep_pre_init,
> -	.init = rcar_gen4_pcie_ep_init,
>  	.raise_irq = rcar_gen4_pcie_ep_raise_irq,
>  	.get_features = rcar_gen4_pcie_ep_get_features,
>  	.get_dbi_offset = rcar_gen4_pcie_ep_get_dbi_offset,
> diff --git a/drivers/pci/controller/dwc/pcie-stm32-ep.c b/drivers/pci/controller/dwc/pcie-stm32-ep.c
> index c1944b40ce02..a7988dff1045 100644
> --- a/drivers/pci/controller/dwc/pcie-stm32-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-stm32-ep.c
> @@ -28,15 +28,6 @@ struct stm32_pcie {
>  	unsigned int perst_irq;
>  };
>
> -static void stm32_pcie_ep_init(struct dw_pcie_ep *ep)
> -{
> -	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> -	enum pci_barno bar;
> -
> -	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
> -		dw_pcie_ep_reset_bar(pci, bar);
> -}
> -
>  static int stm32_pcie_start_link(struct dw_pcie *pci)
>  {
>  	struct stm32_pcie *stm32_pcie = to_stm32_pcie(pci);
> @@ -82,7 +73,6 @@ stm32_pcie_get_features(struct dw_pcie_ep *ep)
>  }
>
>  static const struct dw_pcie_ep_ops stm32_pcie_ep_ops = {
> -	.init = stm32_pcie_ep_init,
>  	.raise_irq = stm32_pcie_raise_irq,
>  	.get_features = stm32_pcie_get_features,
>  };
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index 9f9453e8cd23..3a6bffaff9ea 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -1923,15 +1923,6 @@ static irqreturn_t tegra_pcie_ep_pex_rst_irq(int irq, void *arg)
>  	return IRQ_HANDLED;
>  }
>
> -static void tegra_pcie_ep_init(struct dw_pcie_ep *ep)
> -{
> -	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> -	enum pci_barno bar;
> -
> -	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
> -		dw_pcie_ep_reset_bar(pci, bar);
> -};
> -
>  static int tegra_pcie_ep_raise_intx_irq(struct tegra_pcie_dw *pcie, u16 irq)
>  {
>  	/* Tegra194 supports only INTA */
> @@ -2008,7 +1999,6 @@ tegra_pcie_ep_get_features(struct dw_pcie_ep *ep)
>  }
>
>  static const struct dw_pcie_ep_ops pcie_ep_ops = {
> -	.init = tegra_pcie_ep_init,
>  	.raise_irq = tegra_pcie_ep_raise_irq,
>  	.get_features = tegra_pcie_ep_get_features,
>  };
> diff --git a/drivers/pci/controller/dwc/pcie-uniphier-ep.c b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
> index 5bde3ee682b5..494376d1812d 100644
> --- a/drivers/pci/controller/dwc/pcie-uniphier-ep.c
> +++ b/drivers/pci/controller/dwc/pcie-uniphier-ep.c
> @@ -203,15 +203,6 @@ static void uniphier_pcie_stop_link(struct dw_pcie *pci)
>  	uniphier_pcie_ltssm_enable(priv, false);
>  }
>
> -static void uniphier_pcie_ep_init(struct dw_pcie_ep *ep)
> -{
> -	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> -	enum pci_barno bar;
> -
> -	for (bar = BAR_0; bar <= BAR_5; bar++)
> -		dw_pcie_ep_reset_bar(pci, bar);
> -}
> -
>  static int uniphier_pcie_ep_raise_intx_irq(struct dw_pcie_ep *ep)
>  {
>  	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> @@ -283,7 +274,6 @@ uniphier_pcie_get_features(struct dw_pcie_ep *ep)
>  }
>
>  static const struct dw_pcie_ep_ops uniphier_pcie_ep_ops = {
> -	.init = uniphier_pcie_ep_init,
>  	.raise_irq = uniphier_pcie_ep_raise_irq,
>  	.get_features = uniphier_pcie_get_features,
>  };
> --
> 2.53.0
>

[PATCH 7/9] PCI: endpoint: pci-epf-test: Advertise reserved BARs

[Niklas Cassel]

Advertise reserved BARs as reserved in the Capabilities register,
such that the host side driver will be able to skip reserved BARs.

Signed-off-by: Niklas Cassel <cassel@kernel.org>
---
 drivers/pci/endpoint/functions/pci-epf-test.c | 24 +++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
index 0cb7af0919dc..4c7e42fe5d8e 100644
--- a/drivers/pci/endpoint/functions/pci-epf-test.c
+++ b/drivers/pci/endpoint/functions/pci-epf-test.c
@@ -64,6 +64,12 @@
 #define CAP_MSIX			BIT(2)
 #define CAP_INTX			BIT(3)
 #define CAP_SUBRANGE_MAPPING		BIT(4)
+#define CAP_BAR0_RESERVED		BIT(5)
+#define CAP_BAR1_RESERVED		BIT(6)
+#define CAP_BAR2_RESERVED		BIT(7)
+#define CAP_BAR3_RESERVED		BIT(8)
+#define CAP_BAR4_RESERVED		BIT(9)
+#define CAP_BAR5_RESERVED		BIT(10)
 
 #define PCI_EPF_TEST_BAR_SUBRANGE_NSUB	2
 
@@ -1106,6 +1112,24 @@ static void pci_epf_test_set_capabilities(struct pci_epf *epf)
 	    epf_test->epc_features->subrange_mapping)
 		caps |= CAP_SUBRANGE_MAPPING;
 
+	if (epf_test->epc_features->bar[BAR_0].type == BAR_RESERVED)
+		caps |= CAP_BAR0_RESERVED;
+
+	if (epf_test->epc_features->bar[BAR_1].type == BAR_RESERVED)
+		caps |= CAP_BAR1_RESERVED;
+
+	if (epf_test->epc_features->bar[BAR_2].type == BAR_RESERVED)
+		caps |= CAP_BAR2_RESERVED;
+
+	if (epf_test->epc_features->bar[BAR_3].type == BAR_RESERVED)
+		caps |= CAP_BAR3_RESERVED;
+
+	if (epf_test->epc_features->bar[BAR_4].type == BAR_RESERVED)
+		caps |= CAP_BAR4_RESERVED;
+
+	if (epf_test->epc_features->bar[BAR_5].type == BAR_RESERVED)
+		caps |= CAP_BAR5_RESERVED;
+
 	reg->caps = cpu_to_le32(caps);
 }
 
-- 
2.53.0

Re: [PATCH 7/9] PCI: endpoint: pci-epf-test: Advertise reserved BARs

[Frank Li]

On Tue, Feb 17, 2026 at 10:27:13PM +0100, Niklas Cassel wrote:
> Advertise reserved BARs as reserved in the Capabilities register,
> such that the host side driver will be able to skip reserved BARs.
>
> Signed-off-by: Niklas Cassel <cassel@kernel.org>
> ---
>  drivers/pci/endpoint/functions/pci-epf-test.c | 24 +++++++++++++++++++
>  1 file changed, 24 insertions(+)
>
> diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
> index 0cb7af0919dc..4c7e42fe5d8e 100644
> --- a/drivers/pci/endpoint/functions/pci-epf-test.c
> +++ b/drivers/pci/endpoint/functions/pci-epf-test.c
> @@ -64,6 +64,12 @@
>  #define CAP_MSIX			BIT(2)
>  #define CAP_INTX			BIT(3)
>  #define CAP_SUBRANGE_MAPPING		BIT(4)
> +#define CAP_BAR0_RESERVED		BIT(5)
> +#define CAP_BAR1_RESERVED		BIT(6)
> +#define CAP_BAR2_RESERVED		BIT(7)
> +#define CAP_BAR3_RESERVED		BIT(8)
> +#define CAP_BAR4_RESERVED		BIT(9)
> +#define CAP_BAR5_RESERVED		BIT(10)
>
>  #define PCI_EPF_TEST_BAR_SUBRANGE_NSUB	2
>
> @@ -1106,6 +1112,24 @@ static void pci_epf_test_set_capabilities(struct pci_epf *epf)
>  	    epf_test->epc_features->subrange_mapping)
>  		caps |= CAP_SUBRANGE_MAPPING;
>
> +	if (epf_test->epc_features->bar[BAR_0].type == BAR_RESERVED)
> +		caps |= CAP_BAR0_RESERVED;

Is it BAR_DISABLE? suppose BAR_RESERVED redefine as hardware MMIO mapped
bar

Frank

> +
> +	if (epf_test->epc_features->bar[BAR_1].type == BAR_RESERVED)
> +		caps |= CAP_BAR1_RESERVED;
> +
> +	if (epf_test->epc_features->bar[BAR_2].type == BAR_RESERVED)
> +		caps |= CAP_BAR2_RESERVED;
> +
> +	if (epf_test->epc_features->bar[BAR_3].type == BAR_RESERVED)
> +		caps |= CAP_BAR3_RESERVED;
> +
> +	if (epf_test->epc_features->bar[BAR_4].type == BAR_RESERVED)
> +		caps |= CAP_BAR4_RESERVED;
> +
> +	if (epf_test->epc_features->bar[BAR_5].type == BAR_RESERVED)
> +		caps |= CAP_BAR5_RESERVED;
> +
>  	reg->caps = cpu_to_le32(caps);
>  }
>
> --
> 2.53.0
>

Re: [PATCH 7/9] PCI: endpoint: pci-epf-test: Advertise reserved BARs

[Niklas Cassel]

On Tue, Feb 17, 2026 at 06:02:55PM -0500, Frank Li wrote:
> On Tue, Feb 17, 2026 at 10:27:13PM +0100, Niklas Cassel wrote:
> > Advertise reserved BARs as reserved in the Capabilities register,
> > such that the host side driver will be able to skip reserved BARs.
> >
> > Signed-off-by: Niklas Cassel <cassel@kernel.org>
> > ---
> >  drivers/pci/endpoint/functions/pci-epf-test.c | 24 +++++++++++++++++++
> >  1 file changed, 24 insertions(+)
> >
> > diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
> > index 0cb7af0919dc..4c7e42fe5d8e 100644
> > --- a/drivers/pci/endpoint/functions/pci-epf-test.c
> > +++ b/drivers/pci/endpoint/functions/pci-epf-test.c
> > @@ -64,6 +64,12 @@
> >  #define CAP_MSIX			BIT(2)
> >  #define CAP_INTX			BIT(3)
> >  #define CAP_SUBRANGE_MAPPING		BIT(4)
> > +#define CAP_BAR0_RESERVED		BIT(5)
> > +#define CAP_BAR1_RESERVED		BIT(6)
> > +#define CAP_BAR2_RESERVED		BIT(7)
> > +#define CAP_BAR3_RESERVED		BIT(8)
> > +#define CAP_BAR4_RESERVED		BIT(9)
> > +#define CAP_BAR5_RESERVED		BIT(10)
> >
> >  #define PCI_EPF_TEST_BAR_SUBRANGE_NSUB	2
> >
> > @@ -1106,6 +1112,24 @@ static void pci_epf_test_set_capabilities(struct pci_epf *epf)
> >  	    epf_test->epc_features->subrange_mapping)
> >  		caps |= CAP_SUBRANGE_MAPPING;
> >
> > +	if (epf_test->epc_features->bar[BAR_0].type == BAR_RESERVED)
> > +		caps |= CAP_BAR0_RESERVED;
> 
> Is it BAR_DISABLE? suppose BAR_RESERVED redefine as hardware MMIO mapped
> bar


A BAR that is defined as BAR_DISABLE will always be disabled by the EPC
driver, so the host side driver will not see the BAR in the first place.

If you try to run pci_endpoint_test against a disabled BAR, the size will
be zero, and pci_endpoint_test will return -ENODATA:
https://github.com/torvalds/linux/blob/v6.19/drivers/misc/pci_endpoint_test.c#L300-L302

and the pci_endpoint selftest will print SKIP for that test case.


BAR_RESERVED is describing a BAR that has hardware backed resources, e.g. eDMA
registers, iATU registers, MSI-X table. These BARs are never disabled by an
EPC driver by default. See the kdoc for these enum values here:
https://lore.kernel.org/linux-pci/20260217212707.2450423-15-cassel@kernel.org/


Thus, we need to tell pci_endpoint_test that these reserved BARs (which are
not disabled) has to be skipped, because if we perfrom READ/WRITE tests
against these BARs, bad things will happen. E.g. if you write to a BAR that
exposes iATU registers, you will clear/overwrite the current inbound addresss
translation configured by the endpoint.


Kind regards,
Niklas

Re: [PATCH 7/9] PCI: endpoint: pci-epf-test: Advertise reserved BARs

[Frank Li]

On Wed, Feb 18, 2026 at 11:43:27AM +0100, Niklas Cassel wrote:
> On Tue, Feb 17, 2026 at 06:02:55PM -0500, Frank Li wrote:
> > On Tue, Feb 17, 2026 at 10:27:13PM +0100, Niklas Cassel wrote:
> > > Advertise reserved BARs as reserved in the Capabilities register,
> > > such that the host side driver will be able to skip reserved BARs.
> > >
> > > Signed-off-by: Niklas Cassel <cassel@kernel.org>
> > > ---
> > >  drivers/pci/endpoint/functions/pci-epf-test.c | 24 +++++++++++++++++++
> > >  1 file changed, 24 insertions(+)
> > >
> > > diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c
> > > index 0cb7af0919dc..4c7e42fe5d8e 100644
> > > --- a/drivers/pci/endpoint/functions/pci-epf-test.c
> > > +++ b/drivers/pci/endpoint/functions/pci-epf-test.c
> > > @@ -64,6 +64,12 @@
> > >  #define CAP_MSIX			BIT(2)
> > >  #define CAP_INTX			BIT(3)
> > >  #define CAP_SUBRANGE_MAPPING		BIT(4)
> > > +#define CAP_BAR0_RESERVED		BIT(5)
> > > +#define CAP_BAR1_RESERVED		BIT(6)
> > > +#define CAP_BAR2_RESERVED		BIT(7)
> > > +#define CAP_BAR3_RESERVED		BIT(8)
> > > +#define CAP_BAR4_RESERVED		BIT(9)
> > > +#define CAP_BAR5_RESERVED		BIT(10)
> > >
> > >  #define PCI_EPF_TEST_BAR_SUBRANGE_NSUB	2
> > >
> > > @@ -1106,6 +1112,24 @@ static void pci_epf_test_set_capabilities(struct pci_epf *epf)
> > >  	    epf_test->epc_features->subrange_mapping)
> > >  		caps |= CAP_SUBRANGE_MAPPING;
> > >
> > > +	if (epf_test->epc_features->bar[BAR_0].type == BAR_RESERVED)
> > > +		caps |= CAP_BAR0_RESERVED;
> >
> > Is it BAR_DISABLE? suppose BAR_RESERVED redefine as hardware MMIO mapped
> > bar
>
>
> A BAR that is defined as BAR_DISABLE will always be disabled by the EPC
> driver, so the host side driver will not see the BAR in the first place.
>
> If you try to run pci_endpoint_test against a disabled BAR, the size will
> be zero, and pci_endpoint_test will return -ENODATA:
> https://github.com/torvalds/linux/blob/v6.19/drivers/misc/pci_endpoint_test.c#L300-L302
>
> and the pci_endpoint selftest will print SKIP for that test case.
>
>
> BAR_RESERVED is describing a BAR that has hardware backed resources, e.g. eDMA
> registers, iATU registers, MSI-X table. These BARs are never disabled by an
> EPC driver by default. See the kdoc for these enum values here:
> https://lore.kernel.org/linux-pci/20260217212707.2450423-15-cassel@kernel.org/
>
>
> Thus, we need to tell pci_endpoint_test that these reserved BARs (which are
> not disabled) has to be skipped, because if we perfrom READ/WRITE tests
> against these BARs, bad things will happen. E.g. if you write to a BAR that
> exposes iATU registers, you will clear/overwrite the current inbound addresss
> translation configured by the endpoint.

I see. it actually means skip bar test. is CAP_SKIP_BAR<n>_TEST better?

Frank
>
>
> Kind regards,
> Niklas

Re: [PATCH 7/9] PCI: endpoint: pci-epf-test: Advertise reserved BARs

[Niklas Cassel]

On Wed, Feb 18, 2026 at 11:00:17AM -0500, Frank Li wrote:
> > Thus, we need to tell pci_endpoint_test that these reserved BARs (which are
> > not disabled) has to be skipped, because if we perfrom READ/WRITE tests
> > against these BARs, bad things will happen. E.g. if you write to a BAR that
> > exposes iATU registers, you will clear/overwrite the current inbound addresss
> > translation configured by the endpoint.
> 
> I see. it actually means skip bar test. is CAP_SKIP_BAR<n>_TEST better?

Yes, for pci-epf-test, a reserved BAR should be skipped, but not only for
the BAR<n>_TEST cases, it should also ignore the BAR in the consecutive
BAR test.

Everywhere in drivers/pci/endpoint, a reserved BAR is a BAR with fixed
MMIO registers (to e.g. eDMA registers, MSI-X table, iATU registers).

E.g. the code for the consecutive BAR test in
drivers/misc/pci_endpoint_test.c is:

@@ -403,7 +426,7 @@ static int pci_endpoint_test_bars(struct pci_endpoint_test *test)
 
 	/* Write all BARs in order (without reading). */
 	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
-		if (test->bar[bar])
+		if (test->bar[bar] && !bar_is_reserved(test, bar))
 			pci_endpoint_test_bars_write_bar(test, bar);
 
 	/*


It seems quite clear that pci-epf-test should skip a reserved BAR.

I see your point, but I'm leaning towards that that it is better if we use
the same terminology everywhere.
I'm worried that introducing another terminology (SKIP BAR), might lead to
more confusion than clarity (we already have RESERVED BARs and DISABLED BARs
as enum values in pci_epc_bar_type).


So, while SKIP BAR might be slightly more descriptive for pci-epf-test,
I worry that that using a third term, will cause more harm than good.


Kind regards,
Niklas

Re: [PATCH 7/9] PCI: endpoint: pci-epf-test: Advertise reserved BARs

[Frank Li]

On Thu, Feb 19, 2026 at 10:35:55AM +0100, Niklas Cassel wrote:
> On Wed, Feb 18, 2026 at 11:00:17AM -0500, Frank Li wrote:
> > > Thus, we need to tell pci_endpoint_test that these reserved BARs (which are
> > > not disabled) has to be skipped, because if we perfrom READ/WRITE tests
> > > against these BARs, bad things will happen. E.g. if you write to a BAR that
> > > exposes iATU registers, you will clear/overwrite the current inbound addresss
> > > translation configured by the endpoint.
> >
> > I see. it actually means skip bar test. is CAP_SKIP_BAR<n>_TEST better?
>
> Yes, for pci-epf-test, a reserved BAR should be skipped, but not only for
> the BAR<n>_TEST cases, it should also ignore the BAR in the consecutive
> BAR test.
>
> Everywhere in drivers/pci/endpoint, a reserved BAR is a BAR with fixed
> MMIO registers (to e.g. eDMA registers, MSI-X table, iATU registers).
>
> E.g. the code for the consecutive BAR test in
> drivers/misc/pci_endpoint_test.c is:
>
> @@ -403,7 +426,7 @@ static int pci_endpoint_test_bars(struct pci_endpoint_test *test)
>
>  	/* Write all BARs in order (without reading). */
>  	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
> -		if (test->bar[bar])
> +		if (test->bar[bar] && !bar_is_reserved(test, bar))
>  			pci_endpoint_test_bars_write_bar(test, bar);
>
>  	/*
>
>
> It seems quite clear that pci-epf-test should skip a reserved BAR.
>
> I see your point, but I'm leaning towards that that it is better if we use
> the same terminology everywhere.
> I'm worried that introducing another terminology (SKIP BAR), might lead to
> more confusion than clarity (we already have RESERVED BARs and DISABLED BARs
> as enum values in pci_epc_bar_type).
>
>
> So, while SKIP BAR might be slightly more descriptive for pci-epf-test,
> I worry that that using a third term, will cause more harm than good.

Okay, RESERVED and DISABLED is epf/epc concept to inidcate hardware cap.

pci_endpoint_test is just one usage, skip test RESERVED bar. I am fine
using RESERVED here.

Frank

>
>
> Kind regards,
> Niklas

Re: [PATCH 7/9] PCI: endpoint: pci-epf-test: Advertise reserved BARs

[Manikanta Maddireddy]

Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Tested by: Manikanta Maddireddy <mmaddireddy@nvidia.com>


On 19/02/26 10:42 pm, Frank Li wrote:
> On Thu, Feb 19, 2026 at 10:35:55AM +0100, Niklas Cassel wrote:
>> On Wed, Feb 18, 2026 at 11:00:17AM -0500, Frank Li wrote:
>>>> Thus, we need to tell pci_endpoint_test that these reserved BARs (which are
>>>> not disabled) has to be skipped, because if we perfrom READ/WRITE tests
>>>> against these BARs, bad things will happen. E.g. if you write to a BAR that
>>>> exposes iATU registers, you will clear/overwrite the current inbound addresss
>>>> translation configured by the endpoint.
>>> I see. it actually means skip bar test. is CAP_SKIP_BAR<n>_TEST better?
>> Yes, for pci-epf-test, a reserved BAR should be skipped, but not only for
>> the BAR<n>_TEST cases, it should also ignore the BAR in the consecutive
>> BAR test.
>>
>> Everywhere in drivers/pci/endpoint, a reserved BAR is a BAR with fixed
>> MMIO registers (to e.g. eDMA registers, MSI-X table, iATU registers).
>>
>> E.g. the code for the consecutive BAR test in
>> drivers/misc/pci_endpoint_test.c is:
>>
>> @@ -403,7 +426,7 @@ static int pci_endpoint_test_bars(struct pci_endpoint_test *test)
>>
>>   	/* Write all BARs in order (without reading). */
>>   	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
>> -		if (test->bar[bar])
>> +		if (test->bar[bar] && !bar_is_reserved(test, bar))
>>   			pci_endpoint_test_bars_write_bar(test, bar);
>>
>>   	/*
>>
>>
>> It seems quite clear that pci-epf-test should skip a reserved BAR.
>>
>> I see your point, but I'm leaning towards that that it is better if we use
>> the same terminology everywhere.
>> I'm worried that introducing another terminology (SKIP BAR), might lead to
>> more confusion than clarity (we already have RESERVED BARs and DISABLED BARs
>> as enum values in pci_epc_bar_type).
>>
>>
>> So, while SKIP BAR might be slightly more descriptive for pci-epf-test,
>> I worry that that using a third term, will cause more harm than good.
> Okay, RESERVED and DISABLED is epf/epc concept to inidcate hardware cap.
>
> pci_endpoint_test is just one usage, skip test RESERVED bar. I am fine
> using RESERVED here.
>
> Frank
>
>>
>> Kind regards,
>> Niklas

[PATCH 8/9] misc: pci_endpoint_test: Give reserved BARs a distinct error code

[Niklas Cassel]

Give reserved BARs a distinct error code, such that the pci_endpoint_test
selftest will be able to skip test cases that are run against reserved
BARs.

Signed-off-by: Niklas Cassel <cassel@kernel.org>
---
 drivers/misc/pci_endpoint_test.c | 32 ++++++++++++++++++++++++++++++--
 1 file changed, 30 insertions(+), 2 deletions(-)

diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index 74ab5b5b9011..7cffb6e77c4d 100644
--- a/drivers/misc/pci_endpoint_test.c
+++ b/drivers/misc/pci_endpoint_test.c
@@ -84,6 +84,12 @@
 #define CAP_MSIX				BIT(2)
 #define CAP_INTX				BIT(3)
 #define CAP_SUBRANGE_MAPPING			BIT(4)
+#define CAP_BAR0_RESERVED			BIT(5)
+#define CAP_BAR1_RESERVED			BIT(6)
+#define CAP_BAR2_RESERVED			BIT(7)
+#define CAP_BAR3_RESERVED			BIT(8)
+#define CAP_BAR4_RESERVED			BIT(9)
+#define CAP_BAR5_RESERVED			BIT(10)
 
 #define PCI_ENDPOINT_TEST_DB_BAR		0x34
 #define PCI_ENDPOINT_TEST_DB_OFFSET		0x38
@@ -275,6 +281,23 @@ static int pci_endpoint_test_request_irq(struct pci_endpoint_test *test)
 	return ret;
 }
 
+static bool bar_is_reserved(struct pci_endpoint_test *test, enum pci_barno bar)
+{
+	if (bar == BAR_0 && test->ep_caps & CAP_BAR0_RESERVED)
+		return true;
+	else if (bar == BAR_1 && test->ep_caps & CAP_BAR1_RESERVED)
+		return true;
+	else if (bar == BAR_2 && test->ep_caps & CAP_BAR2_RESERVED)
+		return true;
+	else if (bar == BAR_3 && test->ep_caps & CAP_BAR3_RESERVED)
+		return true;
+	else if (bar == BAR_4 && test->ep_caps & CAP_BAR4_RESERVED)
+		return true;
+	else if (bar == BAR_5 && test->ep_caps & CAP_BAR5_RESERVED)
+		return true;
+	return false;
+}
+
 static const u32 bar_test_pattern[] = {
 	0xA0A0A0A0,
 	0xA1A1A1A1,
@@ -403,7 +426,7 @@ static int pci_endpoint_test_bars(struct pci_endpoint_test *test)
 
 	/* Write all BARs in order (without reading). */
 	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
-		if (test->bar[bar])
+		if (test->bar[bar] && !bar_is_reserved(test, bar))
 			pci_endpoint_test_bars_write_bar(test, bar);
 
 	/*
@@ -413,7 +436,7 @@ static int pci_endpoint_test_bars(struct pci_endpoint_test *test)
 	 * (Reading back the BAR directly after writing can not detect this.)
 	 */
 	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
-		if (test->bar[bar]) {
+		if (test->bar[bar] && !bar_is_reserved(test, bar)) {
 			ret = pci_endpoint_test_bars_read_bar(test, bar);
 			if (ret)
 				return ret;
@@ -1139,6 +1162,11 @@ static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
 		if (is_am654_pci_dev(pdev) && bar == BAR_0)
 			goto ret;
 
+		if (bar_is_reserved(test, bar)) {
+			ret = -ENOBUFS;
+			goto ret;
+		}
+
 		if (cmd == PCITEST_BAR)
 			ret = pci_endpoint_test_bar(test, bar);
 		else
-- 
2.53.0

Re: [PATCH 8/9] misc: pci_endpoint_test: Give reserved BARs a distinct error code

[Niklas Cassel]

On Tue, Feb 17, 2026 at 10:27:14PM +0100, Niklas Cassel wrote:
> Give reserved BARs a distinct error code, such that the pci_endpoint_test
> selftest will be able to skip test cases that are run against reserved
> BARs.
> 
> Signed-off-by: Niklas Cassel <cassel@kernel.org>
> ---
>  drivers/misc/pci_endpoint_test.c | 32 ++++++++++++++++++++++++++++++--
>  1 file changed, 30 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
> index 74ab5b5b9011..7cffb6e77c4d 100644
> --- a/drivers/misc/pci_endpoint_test.c
> +++ b/drivers/misc/pci_endpoint_test.c
> @@ -84,6 +84,12 @@
>  #define CAP_MSIX				BIT(2)
>  #define CAP_INTX				BIT(3)
>  #define CAP_SUBRANGE_MAPPING			BIT(4)
> +#define CAP_BAR0_RESERVED			BIT(5)
> +#define CAP_BAR1_RESERVED			BIT(6)
> +#define CAP_BAR2_RESERVED			BIT(7)
> +#define CAP_BAR3_RESERVED			BIT(8)
> +#define CAP_BAR4_RESERVED			BIT(9)
> +#define CAP_BAR5_RESERVED			BIT(10)
>  
>  #define PCI_ENDPOINT_TEST_DB_BAR		0x34
>  #define PCI_ENDPOINT_TEST_DB_OFFSET		0x38
> @@ -275,6 +281,23 @@ static int pci_endpoint_test_request_irq(struct pci_endpoint_test *test)
>  	return ret;
>  }
>  
> +static bool bar_is_reserved(struct pci_endpoint_test *test, enum pci_barno bar)
> +{
> +	if (bar == BAR_0 && test->ep_caps & CAP_BAR0_RESERVED)
> +		return true;
> +	else if (bar == BAR_1 && test->ep_caps & CAP_BAR1_RESERVED)
> +		return true;
> +	else if (bar == BAR_2 && test->ep_caps & CAP_BAR2_RESERVED)
> +		return true;
> +	else if (bar == BAR_3 && test->ep_caps & CAP_BAR3_RESERVED)
> +		return true;
> +	else if (bar == BAR_4 && test->ep_caps & CAP_BAR4_RESERVED)
> +		return true;
> +	else if (bar == BAR_5 && test->ep_caps & CAP_BAR5_RESERVED)
> +		return true;
> +	return false;

All these "else if" could be replaced with regular "if" since they have
have a return statement inside the if statement.


Kind regards,
Niklas

Re: [PATCH 8/9] misc: pci_endpoint_test: Give reserved BARs a distinct error code

[Frank Li]

On Tue, Feb 17, 2026 at 10:27:14PM +0100, Niklas Cassel wrote:
> Give reserved BARs a distinct error code, such that the pci_endpoint_test
> selftest will be able to skip test cases that are run against reserved
> BARs.
>
> Signed-off-by: Niklas Cassel <cassel@kernel.org>
> ---
>  drivers/misc/pci_endpoint_test.c | 32 ++++++++++++++++++++++++++++++--
>  1 file changed, 30 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
> index 74ab5b5b9011..7cffb6e77c4d 100644
> --- a/drivers/misc/pci_endpoint_test.c
> +++ b/drivers/misc/pci_endpoint_test.c
> @@ -84,6 +84,12 @@
>  #define CAP_MSIX				BIT(2)
>  #define CAP_INTX				BIT(3)
>  #define CAP_SUBRANGE_MAPPING			BIT(4)
> +#define CAP_BAR0_RESERVED			BIT(5)
> +#define CAP_BAR1_RESERVED			BIT(6)
> +#define CAP_BAR2_RESERVED			BIT(7)
> +#define CAP_BAR3_RESERVED			BIT(8)
> +#define CAP_BAR4_RESERVED			BIT(9)
> +#define CAP_BAR5_RESERVED			BIT(10)
>
>  #define PCI_ENDPOINT_TEST_DB_BAR		0x34
>  #define PCI_ENDPOINT_TEST_DB_OFFSET		0x38
> @@ -275,6 +281,23 @@ static int pci_endpoint_test_request_irq(struct pci_endpoint_test *test)
>  	return ret;
>  }
>
> +static bool bar_is_reserved(struct pci_endpoint_test *test, enum pci_barno bar)
> +{
> +	if (bar == BAR_0 && test->ep_caps & CAP_BAR0_RESERVED)
> +		return true;
> +	else if (bar == BAR_1 && test->ep_caps & CAP_BAR1_RESERVED)
> +		return true;
> +	else if (bar == BAR_2 && test->ep_caps & CAP_BAR2_RESERVED)
> +		return true;
> +	else if (bar == BAR_3 && test->ep_caps & CAP_BAR3_RESERVED)
> +		return true;
> +	else if (bar == BAR_4 && test->ep_caps & CAP_BAR4_RESERVED)
> +		return true;
> +	else if (bar == BAR_5 && test->ep_caps & CAP_BAR5_RESERVED)
> +		return true;


return	test->ep_caps & BIT(bar + CAP_BAR0_RESERVED)

Frank

> +	return false;
> +}
> +
>  static const u32 bar_test_pattern[] = {
>  	0xA0A0A0A0,
>  	0xA1A1A1A1,
> @@ -403,7 +426,7 @@ static int pci_endpoint_test_bars(struct pci_endpoint_test *test)
>
>  	/* Write all BARs in order (without reading). */
>  	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
> -		if (test->bar[bar])
> +		if (test->bar[bar] && !bar_is_reserved(test, bar))
>  			pci_endpoint_test_bars_write_bar(test, bar);
>
>  	/*
> @@ -413,7 +436,7 @@ static int pci_endpoint_test_bars(struct pci_endpoint_test *test)
>  	 * (Reading back the BAR directly after writing can not detect this.)
>  	 */
>  	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
> -		if (test->bar[bar]) {
> +		if (test->bar[bar] && !bar_is_reserved(test, bar)) {
>  			ret = pci_endpoint_test_bars_read_bar(test, bar);
>  			if (ret)
>  				return ret;
> @@ -1139,6 +1162,11 @@ static long pci_endpoint_test_ioctl(struct file *file, unsigned int cmd,
>  		if (is_am654_pci_dev(pdev) && bar == BAR_0)
>  			goto ret;
>
> +		if (bar_is_reserved(test, bar)) {
> +			ret = -ENOBUFS;
> +			goto ret;
> +		}
> +
>  		if (cmd == PCITEST_BAR)
>  			ret = pci_endpoint_test_bar(test, bar);
>  		else
> --
> 2.53.0
>

Re: [PATCH 8/9] misc: pci_endpoint_test: Give reserved BARs a distinct error code

[Niklas Cassel]

On Tue, Feb 17, 2026 at 06:07:30PM -0500, Frank Li wrote:
> On Tue, Feb 17, 2026 at 10:27:14PM +0100, Niklas Cassel wrote:
> > Give reserved BARs a distinct error code, such that the pci_endpoint_test
> > selftest will be able to skip test cases that are run against reserved
> > BARs.
> >
> > Signed-off-by: Niklas Cassel <cassel@kernel.org>
> > ---
> >  drivers/misc/pci_endpoint_test.c | 32 ++++++++++++++++++++++++++++++--
> >  1 file changed, 30 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
> > index 74ab5b5b9011..7cffb6e77c4d 100644
> > --- a/drivers/misc/pci_endpoint_test.c
> > +++ b/drivers/misc/pci_endpoint_test.c
> > @@ -84,6 +84,12 @@
> >  #define CAP_MSIX				BIT(2)
> >  #define CAP_INTX				BIT(3)
> >  #define CAP_SUBRANGE_MAPPING			BIT(4)
> > +#define CAP_BAR0_RESERVED			BIT(5)
> > +#define CAP_BAR1_RESERVED			BIT(6)
> > +#define CAP_BAR2_RESERVED			BIT(7)
> > +#define CAP_BAR3_RESERVED			BIT(8)
> > +#define CAP_BAR4_RESERVED			BIT(9)
> > +#define CAP_BAR5_RESERVED			BIT(10)
> >
> >  #define PCI_ENDPOINT_TEST_DB_BAR		0x34
> >  #define PCI_ENDPOINT_TEST_DB_OFFSET		0x38
> > @@ -275,6 +281,23 @@ static int pci_endpoint_test_request_irq(struct pci_endpoint_test *test)
> >  	return ret;
> >  }
> >
> > +static bool bar_is_reserved(struct pci_endpoint_test *test, enum pci_barno bar)
> > +{
> > +	if (bar == BAR_0 && test->ep_caps & CAP_BAR0_RESERVED)
> > +		return true;
> > +	else if (bar == BAR_1 && test->ep_caps & CAP_BAR1_RESERVED)
> > +		return true;
> > +	else if (bar == BAR_2 && test->ep_caps & CAP_BAR2_RESERVED)
> > +		return true;
> > +	else if (bar == BAR_3 && test->ep_caps & CAP_BAR3_RESERVED)
> > +		return true;
> > +	else if (bar == BAR_4 && test->ep_caps & CAP_BAR4_RESERVED)
> > +		return true;
> > +	else if (bar == BAR_5 && test->ep_caps & CAP_BAR5_RESERVED)
> > +		return true;
> 
> 
> return	test->ep_caps & BIT(bar + CAP_BAR0_RESERVED)

Sure, will use that in V2.


Kind regards,
Niklas

Re: [PATCH 8/9] misc: pci_endpoint_test: Give reserved BARs a distinct error code

[Manikanta Maddireddy]

On 18/02/26 4:14 pm, Niklas Cassel wrote:
> On Tue, Feb 17, 2026 at 06:07:30PM -0500, Frank Li wrote:
>> On Tue, Feb 17, 2026 at 10:27:14PM +0100, Niklas Cassel wrote:
>>> Give reserved BARs a distinct error code, such that the pci_endpoint_test
>>> selftest will be able to skip test cases that are run against reserved
>>> BARs.
>>>
>>> Signed-off-by: Niklas Cassel <cassel@kernel.org>
Tested by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>>> ---
>>>   drivers/misc/pci_endpoint_test.c | 32 ++++++++++++++++++++++++++++++--
>>>   1 file changed, 30 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
>>> index 74ab5b5b9011..7cffb6e77c4d 100644
>>> --- a/drivers/misc/pci_endpoint_test.c
>>> +++ b/drivers/misc/pci_endpoint_test.c
>>> @@ -84,6 +84,12 @@
>>>   #define CAP_MSIX				BIT(2)
>>>   #define CAP_INTX				BIT(3)
>>>   #define CAP_SUBRANGE_MAPPING			BIT(4)
>>> +#define CAP_BAR0_RESERVED			BIT(5)
>>> +#define CAP_BAR1_RESERVED			BIT(6)
>>> +#define CAP_BAR2_RESERVED			BIT(7)
>>> +#define CAP_BAR3_RESERVED			BIT(8)
>>> +#define CAP_BAR4_RESERVED			BIT(9)
>>> +#define CAP_BAR5_RESERVED			BIT(10)
>>>
>>>   #define PCI_ENDPOINT_TEST_DB_BAR		0x34
>>>   #define PCI_ENDPOINT_TEST_DB_OFFSET		0x38
>>> @@ -275,6 +281,23 @@ static int pci_endpoint_test_request_irq(struct pci_endpoint_test *test)
>>>   	return ret;
>>>   }
>>>
>>> +static bool bar_is_reserved(struct pci_endpoint_test *test, enum pci_barno bar)
>>> +{
>>> +	if (bar == BAR_0 && test->ep_caps & CAP_BAR0_RESERVED)
>>> +		return true;
>>> +	else if (bar == BAR_1 && test->ep_caps & CAP_BAR1_RESERVED)
>>> +		return true;
>>> +	else if (bar == BAR_2 && test->ep_caps & CAP_BAR2_RESERVED)
>>> +		return true;
>>> +	else if (bar == BAR_3 && test->ep_caps & CAP_BAR3_RESERVED)
>>> +		return true;
>>> +	else if (bar == BAR_4 && test->ep_caps & CAP_BAR4_RESERVED)
>>> +		return true;
>>> +	else if (bar == BAR_5 && test->ep_caps & CAP_BAR5_RESERVED)
>>> +		return true;
>>
>> return	test->ep_caps & BIT(bar + CAP_BAR0_RESERVED)
I think it should be
return !!(test->ep_caps & BIT(bar + CAP_BAR0_RESERVED))
> Sure, will use that in V2.
>
>
> Kind regards,
> Niklas

Re: [PATCH 8/9] misc: pci_endpoint_test: Give reserved BARs a distinct error code

[Niklas Cassel]

On Mon, Feb 23, 2026 at 10:30:39AM +0530, Manikanta Maddireddy wrote:
> 
> On 18/02/26 4:14 pm, Niklas Cassel wrote:
> > On Tue, Feb 17, 2026 at 06:07:30PM -0500, Frank Li wrote:
> > > On Tue, Feb 17, 2026 at 10:27:14PM +0100, Niklas Cassel wrote:
> > > > Give reserved BARs a distinct error code, such that the pci_endpoint_test
> > > > selftest will be able to skip test cases that are run against reserved
> > > > BARs.
> > > > 
> > > > Signed-off-by: Niklas Cassel <cassel@kernel.org>
> Tested by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
> > > > ---
> > > >   drivers/misc/pci_endpoint_test.c | 32 ++++++++++++++++++++++++++++++--
> > > >   1 file changed, 30 insertions(+), 2 deletions(-)
> > > > 
> > > > diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
> > > > index 74ab5b5b9011..7cffb6e77c4d 100644
> > > > --- a/drivers/misc/pci_endpoint_test.c
> > > > +++ b/drivers/misc/pci_endpoint_test.c
> > > > @@ -84,6 +84,12 @@
> > > >   #define CAP_MSIX				BIT(2)
> > > >   #define CAP_INTX				BIT(3)
> > > >   #define CAP_SUBRANGE_MAPPING			BIT(4)
> > > > +#define CAP_BAR0_RESERVED			BIT(5)
> > > > +#define CAP_BAR1_RESERVED			BIT(6)
> > > > +#define CAP_BAR2_RESERVED			BIT(7)
> > > > +#define CAP_BAR3_RESERVED			BIT(8)
> > > > +#define CAP_BAR4_RESERVED			BIT(9)
> > > > +#define CAP_BAR5_RESERVED			BIT(10)
> > > > 
> > > >   #define PCI_ENDPOINT_TEST_DB_BAR		0x34
> > > >   #define PCI_ENDPOINT_TEST_DB_OFFSET		0x38
> > > > @@ -275,6 +281,23 @@ static int pci_endpoint_test_request_irq(struct pci_endpoint_test *test)
> > > >   	return ret;
> > > >   }
> > > > 
> > > > +static bool bar_is_reserved(struct pci_endpoint_test *test, enum pci_barno bar)
> > > > +{
> > > > +	if (bar == BAR_0 && test->ep_caps & CAP_BAR0_RESERVED)
> > > > +		return true;
> > > > +	else if (bar == BAR_1 && test->ep_caps & CAP_BAR1_RESERVED)
> > > > +		return true;
> > > > +	else if (bar == BAR_2 && test->ep_caps & CAP_BAR2_RESERVED)
> > > > +		return true;
> > > > +	else if (bar == BAR_3 && test->ep_caps & CAP_BAR3_RESERVED)
> > > > +		return true;
> > > > +	else if (bar == BAR_4 && test->ep_caps & CAP_BAR4_RESERVED)
> > > > +		return true;
> > > > +	else if (bar == BAR_5 && test->ep_caps & CAP_BAR5_RESERVED)
> > > > +		return true;
> > > 
> > > return	test->ep_caps & BIT(bar + CAP_BAR0_RESERVED)
> I think it should be
> return !!(test->ep_caps & BIT(bar + CAP_BAR0_RESERVED))

I don't think !! is needed:

"When any scalar value is converted to _Bool, the result is 0 if the value
compares equal to 0; otherwise, the result is 1."


Kind regards,
Niklas

[PATCH 9/9] selftests: pci_endpoint: Skip reserved BARs

[Niklas Cassel]

Running a test against a reserved BAR will result in the pci-epf-test
driver returning -ENOBUFS.

Make sure that the pci_endpoint_test selftest will return skip instead of
failure or success for reserved BARs.

Signed-off-by: Niklas Cassel <cassel@kernel.org>
---
 tools/testing/selftests/pci_endpoint/pci_endpoint_test.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/tools/testing/selftests/pci_endpoint/pci_endpoint_test.c b/tools/testing/selftests/pci_endpoint/pci_endpoint_test.c
index eecb776c33af..e506359cdded 100644
--- a/tools/testing/selftests/pci_endpoint/pci_endpoint_test.c
+++ b/tools/testing/selftests/pci_endpoint/pci_endpoint_test.c
@@ -67,6 +67,8 @@ TEST_F(pci_ep_bar, BAR_TEST)
 	pci_ep_ioctl(PCITEST_BAR, variant->barno);
 	if (ret == -ENODATA)
 		SKIP(return, "BAR is disabled");
+	if (ret == -ENOBUFS)
+		SKIP(return, "BAR is reserved");
 	EXPECT_FALSE(ret) TH_LOG("Test failed for BAR%d", variant->barno);
 }
 
@@ -84,6 +86,8 @@ TEST_F(pci_ep_bar, BAR_SUBRANGE_TEST)
 		SKIP(return, "BAR is test register space");
 	if (ret == -EOPNOTSUPP)
 		SKIP(return, "Subrange map is not supported");
+	if (ret == -ENOBUFS)
+		SKIP(return, "BAR is reserved");
 	EXPECT_FALSE(ret) TH_LOG("Test failed for BAR%d", variant->barno);
 }
 
-- 
2.53.0

Re: [PATCH 9/9] selftests: pci_endpoint: Skip reserved BARs

[Frank Li]

On Tue, Feb 17, 2026 at 10:27:15PM +0100, Niklas Cassel wrote:
> Running a test against a reserved BAR will result in the pci-epf-test
> driver returning -ENOBUFS.
>
> Make sure that the pci_endpoint_test selftest will return skip instead of
> failure or success for reserved BARs.
>
> Signed-off-by: Niklas Cassel <cassel@kernel.org>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

>  tools/testing/selftests/pci_endpoint/pci_endpoint_test.c | 4 ++++
>  1 file changed, 4 insertions(+)
>
> diff --git a/tools/testing/selftests/pci_endpoint/pci_endpoint_test.c b/tools/testing/selftests/pci_endpoint/pci_endpoint_test.c
> index eecb776c33af..e506359cdded 100644
> --- a/tools/testing/selftests/pci_endpoint/pci_endpoint_test.c
> +++ b/tools/testing/selftests/pci_endpoint/pci_endpoint_test.c
> @@ -67,6 +67,8 @@ TEST_F(pci_ep_bar, BAR_TEST)
>  	pci_ep_ioctl(PCITEST_BAR, variant->barno);
>  	if (ret == -ENODATA)
>  		SKIP(return, "BAR is disabled");
> +	if (ret == -ENOBUFS)
> +		SKIP(return, "BAR is reserved");
>  	EXPECT_FALSE(ret) TH_LOG("Test failed for BAR%d", variant->barno);
>  }
>
> @@ -84,6 +86,8 @@ TEST_F(pci_ep_bar, BAR_SUBRANGE_TEST)
>  		SKIP(return, "BAR is test register space");
>  	if (ret == -EOPNOTSUPP)
>  		SKIP(return, "Subrange map is not supported");
> +	if (ret == -ENOBUFS)
> +		SKIP(return, "BAR is reserved");
>  	EXPECT_FALSE(ret) TH_LOG("Test failed for BAR%d", variant->barno);
>  }
>
> --
> 2.53.0
>

Re: [PATCH 9/9] selftests: pci_endpoint: Skip reserved BARs

[Manikanta Maddireddy]

On 18/02/26 4:41 am, Frank Li wrote:
> On Tue, Feb 17, 2026 at 10:27:15PM +0100, Niklas Cassel wrote:
>> Running a test against a reserved BAR will result in the pci-epf-test
>> driver returning -ENOBUFS.
>>
>> Make sure that the pci_endpoint_test selftest will return skip instead of
>> failure or success for reserved BARs.
>>
>> Signed-off-by: Niklas Cassel <cassel@kernel.org>
>> ---
> Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Tested by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
>>   tools/testing/selftests/pci_endpoint/pci_endpoint_test.c | 4 ++++
>>   1 file changed, 4 insertions(+)
>>
>> diff --git a/tools/testing/selftests/pci_endpoint/pci_endpoint_test.c b/tools/testing/selftests/pci_endpoint/pci_endpoint_test.c
>> index eecb776c33af..e506359cdded 100644
>> --- a/tools/testing/selftests/pci_endpoint/pci_endpoint_test.c
>> +++ b/tools/testing/selftests/pci_endpoint/pci_endpoint_test.c
>> @@ -67,6 +67,8 @@ TEST_F(pci_ep_bar, BAR_TEST)
>>   	pci_ep_ioctl(PCITEST_BAR, variant->barno);
>>   	if (ret == -ENODATA)
>>   		SKIP(return, "BAR is disabled");
>> +	if (ret == -ENOBUFS)
>> +		SKIP(return, "BAR is reserved");
>>   	EXPECT_FALSE(ret) TH_LOG("Test failed for BAR%d", variant->barno);
>>   }
>>
>> @@ -84,6 +86,8 @@ TEST_F(pci_ep_bar, BAR_SUBRANGE_TEST)
>>   		SKIP(return, "BAR is test register space");
>>   	if (ret == -EOPNOTSUPP)
>>   		SKIP(return, "Subrange map is not supported");
>> +	if (ret == -ENOBUFS)
>> +		SKIP(return, "BAR is reserved");
>>   	EXPECT_FALSE(ret) TH_LOG("Test failed for BAR%d", variant->barno);
>>   }
>>
>> --
>> 2.53.0
>>

Re: [PATCH 0/9] PCI: endpoint differentiate between disabled and reserved BARs

[Manikanta Maddireddy]

On 18/02/26 2:57 am, Niklas Cassel wrote:
> Hello all,
>
> This series is written in response to the patch series from
> Manikanta Maddireddy that was posted here:
> https://lore.kernel.org/linux-pci/291dab65-3fa6-4fc8-90a2-4ad608ca015c@nvidia.com/T/#t
>
> The reasons why I decided to post this a new series was because the series
> above:
>
> 1) Adds PCI device and vendor specific code to
> drivers/misc/pci_endpoint_test.c. We've worked hard to make sure that
> device specific quirks/limitations are communicated via the Capabilities
> register, so let's do the same for reserved BARs.
>
> 2) My review comment which suggested to convert all uses of BAR_RESERVED
> to BAR_DISABLED (except for pci-keystone.c) was ignored.
>
> 3) Koichiro has posted a series that allows an EPC driver to define exactly
> which hardware backed resources are provided in a BAR_RESERVED BAR. Yet,
> this nice improvement was not incorporated. (While Mankata was part of the
> discussion, he was not CC:d on the patches that actually implemented this.)
>
> 4) The selftests should return skip instead of silent success for a
> reserved BAR.
>
> 5) As Mankata points out, but did not address, BAR_RESERVED is quite
> ambiguous, so it is better to introduce a new BAR_64BIT_UPPER to more
> clearly mark the upper part of a 64-bit BAR as this, rather than reuse
> BAR_RESERVED.
>
> 6) It is possible to remove all the dw_pcie_ep_reset_bar() calls in the
> DWC based glue drivers and move it to DWC common code.
>
>
> Because of all of the above, I thought it was just easier to post a series
> with all of the above addressed, as it seemed easier to just show what I
> meant rather than to try to explain things with words.
>
> The thing that is missing is to add a patch for pcie-tegra194.c which
> converts the BARs to BAR_RESERVED.
> Please see patch "PCI: dw-rockchip: Describe RK3588 BAR4 DMA ctrl window"
> and do something similar to pcie-tegra194.c.
>
> If we are missing some resources (right now we only have
> PCI_EPC_BAR_RSVD_DMA_CTRL_MMIO), then I think we should simple add that
> (e.g. PCI_EPC_BAR_RSVD_MSIX).
>
> Mankata, it would be nice if you could test this series, and if you could
> provide a pcie-tegra194.c patch that adds the sizes of the eDMA regs +
> MSI-X table in BAR_2 and BAR_4.
>
>
> Kind regards,
> Niklas
>
>
> Koichiro Den (2):
>    PCI: endpoint: Describe reserved subregions within BARs
>    PCI: dw-rockchip: Describe RK3588 BAR4 DMA ctrl window
>
> Niklas Cassel (7):
>    PCI: endpoint: Introduce pci_epc_bar_type BAR_64BIT_UPPER
>    PCI: endpoint: Introduce pci_epc_bar_type BAR_DISABLED
>    PCI: dwc: Replace BAR_RESERVED with BAR_DISABLED in glue drivers
>    PCI: dwc: Disable BARs in common code instead of in each glue driver
>    PCI: endpoint: pci-epf-test: Advertise reserved BARs
>    misc: pci_endpoint_test: Give reserved BARs a distinct error code
>    selftests: pci_endpoint: Skip reserved BARs
>
>   drivers/misc/pci_endpoint_test.c              | 32 ++++++++++++-
>   drivers/pci/controller/dwc/pci-dra7xx.c       |  4 --
>   drivers/pci/controller/dwc/pci-imx6.c         | 22 +++------
>   .../pci/controller/dwc/pci-layerscape-ep.c    |  8 +---
>   drivers/pci/controller/dwc/pcie-artpec6.c     |  4 --
>   .../pci/controller/dwc/pcie-designware-ep.c   | 24 ++++++++++
>   .../pci/controller/dwc/pcie-designware-plat.c | 10 -----
>   drivers/pci/controller/dwc/pcie-dw-rockchip.c | 19 +++++---
>   drivers/pci/controller/dwc/pcie-keembay.c     |  6 +--
>   drivers/pci/controller/dwc/pcie-qcom-ep.c     | 14 +-----
>   drivers/pci/controller/dwc/pcie-rcar-gen4.c   | 16 ++-----
>   drivers/pci/controller/dwc/pcie-stm32-ep.c    | 10 -----
>   drivers/pci/controller/dwc/pcie-tegra194.c    | 20 +++------
>   drivers/pci/controller/dwc/pcie-uniphier-ep.c | 24 +++-------
>   drivers/pci/controller/pcie-rcar-ep.c         |  6 +--
>   drivers/pci/endpoint/functions/pci-epf-test.c | 24 ++++++++++
>   drivers/pci/endpoint/pci-epc-core.c           |  6 ++-
>   include/linux/pci-epc.h                       | 45 +++++++++++++++++--
>   .../pci_endpoint/pci_endpoint_test.c          |  4 ++
>   19 files changed, 173 insertions(+), 125 deletions(-)
>
Hi Niklas,

I verified this patch series, along with the one linked below, on the 
Jetson AGX Orin platform:
https://lore.kernel.org/linux-pci/20260222193456.2460963-1-mmaddireddy@nvidia.com/T/#t

I reviewed the BAR details in the lspci -vvv output—all three BARs are 
enabled.
I also ran pci_endpoint_test, and all tests passed successfully.

Thanks,
Manikanta