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From: Inochi Amaoto <inochiama@gmail.com>
To: "Yao Zi" <me@ziyao.cc>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Siddharth Vadapalli" <s-vadapalli@ti.com>,
	"Hans Zhang" <18255117159@163.com>,
	"Kishon Vijay Abraham I" <kishon@kernel.org>,
	"Chen Wang" <unicorn_wang@outlook.com>,
	"Manikandan K Pillai" <mpillai@cadence.com>,
	"Christophe JAILLET" <christophe.jaillet@wanadoo.fr>,
	"Inochi Amaoto" <inochiama@gmail.com>,
	"Han Gao" <rabenda.cn@gmail.com>
Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/2] PCI: cadence: Support platform-specific hooks for RC init/deinit
Date: Tue, 3 Mar 2026 09:08:53 +0800	[thread overview]
Message-ID: <aaY0kWYTZx3zs3o7@inochi.infowork> (raw)
In-Reply-To: <20260227181925.52475-2-me@ziyao.cc>

On Fri, Feb 27, 2026 at 06:19:24PM +0000, Yao Zi wrote:
> Support initialization and de-initialization hooks provided by
> platform-specific drivers. Initialization ones run after everything
> else has been set up for RC, but before it's probed by the PCI
> subsystem, to allow platform drivers to easily override RC properties
> like LNKCAP. De-initialization ones run before anything else has been
> cleaned-up.
> 
> Signed-off-by: Yao Zi <me@ziyao.cc>
> ---
>  drivers/pci/controller/cadence/pcie-cadence-host.c | 8 +++++++-
>  drivers/pci/controller/cadence/pcie-cadence.h      | 7 +++++++
>  2 files changed, 14 insertions(+), 1 deletion(-)
> 

LGTM.

Reviewed-by: Inochi Amaoto <inochiama@gmail.com>

Regards,
Inochi

> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c
> index db3154c1eccb..23ee5a9c240d 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence-host.c
> +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c
> @@ -304,6 +304,8 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc)
>  
>  static void cdns_pcie_host_deinit(struct cdns_pcie_rc *rc)
>  {
> +	if (rc->ops->deinit)
> +		rc->ops->deinit(rc);
>  	cdns_pcie_host_deinit_address_translation(rc);
>  	cdns_pcie_host_deinit_root_port(rc);
>  }
> @@ -316,7 +318,11 @@ int cdns_pcie_host_init(struct cdns_pcie_rc *rc)
>  	if (err)
>  		return err;
>  
> -	return cdns_pcie_host_init_address_translation(rc);
> +	err = cdns_pcie_host_init_address_translation(rc);
> +	if (err)
> +		return err;
> +
> +	return rc->ops->init ? rc->ops->init(rc) : 0;
>  }
>  EXPORT_SYMBOL_GPL(cdns_pcie_host_init);
>  
> diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h
> index 443033c607d7..7d8f8e87915b 100644
> --- a/drivers/pci/controller/cadence/pcie-cadence.h
> +++ b/drivers/pci/controller/cadence/pcie-cadence.h
> @@ -100,6 +100,11 @@ struct cdns_pcie {
>  	const  struct cdns_plat_pcie_of_data *cdns_pcie_reg_offsets;
>  };
>  
> +struct cdns_pcie_rc_ops {
> +	int	(*init)(struct cdns_pcie_rc *rc);
> +	void	(*deinit)(struct cdns_pcie_rc *rc);
> +};
> +
>  /**
>   * struct cdns_pcie_rc - private data for this PCIe Root Complex driver
>   * @pcie: Cadence PCIe controller
> @@ -115,6 +120,7 @@ struct cdns_pcie {
>   * @quirk_detect_quiet_flag: LTSSM Detect Quiet min delay set as quirk
>   * @ecam_supported: Whether the ECAM is supported
>   * @no_inbound_map: Whether inbound mapping is supported
> + * @ops: Platform-specific hooks to initialize/de-initialize PCIe Root Complex
>   */
>  struct cdns_pcie_rc {
>  	struct cdns_pcie	pcie;
> @@ -127,6 +133,7 @@ struct cdns_pcie_rc {
>  	unsigned int		quirk_detect_quiet_flag:1;
>  	unsigned int            ecam_supported:1;
>  	unsigned int            no_inbound_map:1;
> +	const struct cdns_pcie_rc_ops *ops;
>  };
>  
>  /**
> -- 
> 2.53.0
> 

  reply	other threads:[~2026-03-03  1:09 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-27 18:19 [PATCH v2 0/2] PCI/sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports Yao Zi
2026-02-27 18:19 ` [PATCH v2 1/2] PCI: cadence: Support platform-specific hooks for RC init/deinit Yao Zi
2026-03-03  1:08   ` Inochi Amaoto [this message]
2026-03-03  6:34   ` Chen Wang
2026-02-27 18:19 ` [PATCH v2 2/2] PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports Yao Zi
2026-02-27 18:24   ` Yao Zi
2026-03-03  1:09     ` Inochi Amaoto
2026-03-03  6:37   ` Chen Wang
2026-03-26 16:45   ` Manivannan Sadhasivam
2026-03-27  8:19     ` Yao Zi

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