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X-CSE-ConnectionGUID: fQDzmUhDTZWYrcekiog6cg== X-CSE-MsgGUID: Y8vUJJ7sQ9Wlk2zRS/pYzg== X-IronPort-AV: E=McAfee;i="6800,10657,11724"; a="85662785" X-IronPort-AV: E=Sophos;i="6.23,112,1770624000"; d="scan'208";a="85662785" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Mar 2026 04:37:46 -0700 X-CSE-ConnectionGUID: WKFysl9bQC2xmFKIChwLoQ== X-CSE-MsgGUID: CHngzzXkTCCp14kBfXf1qQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,112,1770624000"; d="scan'208";a="243099015" Received: from zzombora-mobl1 (HELO localhost) ([10.245.244.33]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Mar 2026 04:37:43 -0700 Date: Tue, 10 Mar 2026 13:37:40 +0200 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Simon Richter Cc: linux-pci@vger.kernel.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org Subject: Re: [PATCH v3 4/5] pci: check if VGA decoding was really activated Message-ID: References: <20260307173538.763188-1-Simon.Richter@hogyros.de> <20260307173538.763188-5-Simon.Richter@hogyros.de> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20260307173538.763188-5-Simon.Richter@hogyros.de> X-Patchwork-Hint: comment Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs Bertel Jungin Aukio 5, 02600 Espoo, Finland On Sun, Mar 08, 2026 at 02:35:37AM +0900, Simon Richter wrote: > PCI bridges are allowed to refuse activating VGA decoding, by simply > ignoring attempts to set the bit that enables it, so after setting the bit, > read it back to verify. > > One example of such a bridge is the root bridge in IBM PowerNV, but this is > also useful for GPU passthrough into virtual machines, where it is > difficult to set up routing for legacy IO through IOMMU. > > Signed-off-by: Simon Richter > --- > drivers/pci/pci.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c > index 8479c2e1f74f..e60b948f8576 100644 > --- a/drivers/pci/pci.c > +++ b/drivers/pci/pci.c > @@ -6197,6 +6197,12 @@ int pci_set_vga_state(struct pci_dev *dev, bool decode, > cmd &= ~PCI_BRIDGE_CTL_VGA; > pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, > cmd); > + if (decode) { > + pci_read_config_word(bridge, PCI_BRIDGE_CONTROL, > + &cmd); > + if(!(cmd & PCI_BRIDGE_CTL_VGA)) > + return -EIO; > + } Maybe this should also have a comment or spec quote to explain that it's legal behavior? The slightly bigger concern I have is whether we need to unwind the previous steps if this fails? Looks like we don't update vgadev->owns on failure (even though we may have partially enabled things). But since the bridge should never forward any VGA accesses, leaving some extra PCI_COMMAND enable(s) set on the device shouldn't matter in practice. So I guess this should work even without unwinding. Well, not sure about arch_set_vga_state() since that's 100% magic... > } > bus = bus->parent; > } > -- > 2.47.3 -- Ville Syrjälä Intel