Re: PCI: Enforce bus address limits in resource allocation

[Daniel Walker <danielwa@cisco.com>]

Hi,

Please forgive my ignorance of PCI. I know very little about it, but 
I'll try to convey the issue I'm seeing.

I have a powerpc system with PCI, and some devices attached to the PCI 
bus. In 3.10 everything worked fine, then we moved to 4.9 and we had 
some issues. I was able to bisect the issue down to the patch in the 
subject line.

f75b99d PCI: Enforce bus address limits in resource allocation


 From 3.10 here is part of the PCI initialization,

|pci 0001:0e:00.0: BAR 0: assigned [mem 0xfc0000000-0xfc00fffff pref]|
|pci 0001:07:09.0: PCI bridge to [bus 0e]|
|pci 0001:07:09.0: bridge window [mem 0xfc0000000-0xfc00fffff 64bit pref]|
         
       
|||In this section the memory resource for the bridge is 64bit, and the 
device "BAR 0" gets a 64bit range. However, it seems the device is 32bit.|
||
|Now fast forward to 4.9 we get this,|

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|
pci 0001:0e:00.0: BAR 0: no space for [mem size 0x00100000 pref]
pci 0001:0e:00.0: BAR 0: failed to assign [mem size 0x00100000 pref]
pci 0001:07:09.0: PCI bridge to [bus 0e]
pci 0001:07:09.0: bridge window [mem 0xfc0000000-0xfc00fffff 64bit pref]

|
|Here it seems to have a larger size, I'm not sure where the size is 
coming from. I was able to work around the issue by setting 
IORESOURCE_MEM_64 on the resource for this device. I also was able to 
work around it by setting "max = avail.end" to "max = (-1);" inside 
pci_bus_alloc_resource(). |
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||I don't know if the problem is the patch, or something else inside our 
system, but any thoughts are appreciated.

Daniel
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