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[2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id z1-20020ac24181000000b004db3900da02sm630723lfh.73.2023.05.06.05.01.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 06 May 2023 05:01:20 -0700 (PDT) Message-ID: Date: Sat, 6 May 2023 15:01:19 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH 4/8] PCI: qcom: Do not advertise hotplug capability for IPs v2.3.3 and v2.9.0 Content-Language: en-GB To: Manivannan Sadhasivam , lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, steev@kali.org, quic_srichara@quicinc.com References: <20230506073139.8789-1-manivannan.sadhasivam@linaro.org> <20230506073139.8789-5-manivannan.sadhasivam@linaro.org> From: Dmitry Baryshkov In-Reply-To: <20230506073139.8789-5-manivannan.sadhasivam@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On 06/05/2023 10:31, Manivannan Sadhasivam wrote: > SoCs making use of Qcom PCIe controller IPs v2.3.3 and v2.9.0 do not > support hotplug functionality. But the hotplug capability bit is set by > default in the hardware. This causes the kernel PCI core to register > hotplug service for the controller and send hotplug commands to it. But > those commands will timeout generating messages as below during boot > and suspend/resume. > > [ 5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2020 msec ago) > [ 5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2048 msec ago) > [ 7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2020 msec ago) > [ 7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2052 msec ago) > > This not only spams the console output but also induces a delay of a > couple of seconds. To fix this issue, let's not set the HPC bit in > PCI_EXP_SLTCAP register as a part of the post init sequence to not > advertise the hotplug capability for the controller. > > Signed-off-by: Manivannan Sadhasivam > --- > drivers/pci/controller/dwc/pcie-qcom.c | 1 - > 1 file changed, 1 deletion(-) Reviewed-by: Dmitry Baryshkov -- With best wishes Dmitry