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charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On 2/14/23 23:08, Rick Wertenbroek wrote: > The RK3399 PCIe controller should wait until the PHY PLLs are locked. > Add poll and timeout to wait for PHY PLLs to be locked. If they cannot > be locked generate error message and jump to error handler. Accessing > registers in the PHY clock domain when PLLs are not locked causes hang > The PHY PLLs status is checked through a side channel register. > This is documented in the TRM section 17.5.8.1 "PCIe Initialization > Sequence". > > Fixes: cf590b078391 ("PCI: rockchip: Add EP driver for Rockchip PCIe controller") > Cc: stable@vger.kernel.org > Signed-off-by: Rick Wertenbroek A couple of nits below. Otherwise: Reviewed-by: Damien Le Moal Tested-by: Damien Le Moal > --- > drivers/pci/controller/pcie-rockchip.c | 16 ++++++++++++++++ > drivers/pci/controller/pcie-rockchip.h | 2 ++ > 2 files changed, 18 insertions(+) > > diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c > index 990a00e08..5f2e2dd5d 100644 > --- a/drivers/pci/controller/pcie-rockchip.c > +++ b/drivers/pci/controller/pcie-rockchip.c [...] > + err = readx_poll_timeout(rockchip_pcie_read_addr, PCIE_CLIENT_SIDE_BAND_STATUS, Nit: long line. Split it after the first comma. > + regs, !(regs & PCIE_CLIENT_PHY_ST), RK_PHY_PLL_LOCK_SLEEP_US, > + RK_PHY_PLL_LOCK_TIMEOUT_US); > + Nit: no need for this blank line. > + if (err) { > + dev_err(dev, "PHY PLLs could not lock, %d\n", err); > + goto err_power_off_phy; > + } > + -- Damien Le Moal Western Digital Research