Re: [PATCH v3] PCI: Skip Target Speed quirk on clamped ports with no link

[Aoxtj <aoxiangtianji@axtjblog.cc>]

On 2026/8/8 14:31, Andreas Wild wrote:
> Expected output:
>
> - "diag: pre" gives the error the retrain returned and whether the
>    link was already down at that point.
> - "diag: post DLLLA=1 after <n>ms" would mean the link does come back,
>    just not before pci_device_add() returns and the bus below is
>    scanned.  That would point at the error path needing to wait for
>    DLLLA rather than only for the Link Training bit to clear.
> - "diag: post DLLLA=0 after 1000ms" would mean the link is genuinely
>    down and staying down, which is a different problem and
>    probably a worse one.
>
> One caveat: the poll loop waits up to a second in the error path, so it
> changes timing.  If the diagnostic build happens to boot reliably where
> the plain v3 build did not, that is also worth reporting.
Diagnostic result: link is genuinely down, not recovering.

Tested 7.0.14-8-pve++ (v3 patch + diagnostic patch) on the same machine. 
Boot fails: SK hynix never enumerates on bus 07.

[0.542354] pci 0000:00:02.4: removing 2.5GT/s downstream link speed 
restriction
[1.623696] pci 0000:00:02.4: retraining failed
[1.623701] diag: pre  ret=-110 DLLLA=0 sta=0x9023 ctl2=0x0023
[3.734697] diag: post DLLLA=0 after 1010ms sta=0x9823
[3.734702] diag: post ctl2=0x0021

Sorry for taking so long to reply; I've been a little busy this week. 
Happy to test anything else.