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Sat, 09 May 2026 00:18:32 -0700 (PDT) Date: Sat, 9 May 2026 15:18:11 +0800 From: Inochi Amaoto To: Rob Herring , Inochi Amaoto Cc: Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Alex Elder , Gustavo Pimentel , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Yixun Lan , Longbin Li Subject: Re: [PATCH 4/5] dt-bindings: pci: spacemit: Introduce Spacemit K3 PCIe host controller Message-ID: References: <20260502101319.2364052-1-inochiama@gmail.com> <20260502101319.2364052-5-inochiama@gmail.com> <20260507191302.GA2284447-robh@kernel.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260507191302.GA2284447-robh@kernel.org> On Thu, May 07, 2026 at 02:13:02PM -0500, Rob Herring wrote: > On Sat, May 02, 2026 at 06:13:17PM +0800, Inochi Amaoto wrote: > > Add binding support for the PCIe controller on the SpacemiT K3 SoC. > > This controller is almost a standard Synopsys Designware PCIe IP, > > with some extra link and reset state control. > > > > Signed-off-by: Inochi Amaoto > > --- > > .../bindings/pci/spacemit,k3-pcie-host.yaml | 142 ++++++++++++++++++ > > 1 file changed, 142 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/pci/spacemit,k3-pcie-host.yaml > > > > diff --git a/Documentation/devicetree/bindings/pci/spacemit,k3-pcie-host.yaml b/Documentation/devicetree/bindings/pci/spacemit,k3-pcie-host.yaml > > new file mode 100644 > > index 000000000000..be2641526b19 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pci/spacemit,k3-pcie-host.yaml > > @@ -0,0 +1,142 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/pci/spacemit,k3-pcie-host.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: SpacemiT K3 PCI Express Host Controller > > + > > +maintainers: > > + - Inochi Amaoto > > + > > +description: > > + The SpacemiT K3 SoC PCIe host controller is based on the Synopsys > > + DesignWare PCIe IP. The controller uses the external MSI interrupt > > + controller. > > + > > +allOf: > > + - $ref: /schemas/pci/pci-host-bridge.yaml# > > + - $ref: /schemas/pci/snps,dw-pcie.yaml# > > + > > +properties: > > + compatible: > > + const: spacemit,k3-pcie > > + > > + reg: > > + items: > > + - description: DesignWare PCIe registers > > + - description: Data Bus Interface (DBI) shadow registers > > + - description: ATU address space > > + - description: PCIe configuration space > > + - description: Link control registers > > + > > + reg-names: > > + items: > > + - const: dbi > > + - const: dbi2 > > + - const: atu > > + - const: config > > + - const: link > > + > > + clocks: > > + items: > > + - description: DWC PCIe Data Bus Interface (DBI) clock > > + - description: DWC PCIe application AXI-bus master interface clock > > + - description: DWC PCIe application AXI-bus slave interface clock > > + > > + clock-names: > > + items: > > + - const: dbi > > + - const: mstr > > + - const: slv > > + > > + resets: > > + items: > > + - description: DWC PCIe Data Bus Interface (DBI) reset > > + - description: DWC PCIe application AXI-bus master interface reset > > + - description: DWC PCIe application AXI-bus slave interface reset > > + > > + reset-names: > > + items: > > + - const: dbi > > + - const: mstr > > + - const: slv > > + > > + interrupts: > > + items: > > + - description: Interrupt used for port state > > + > > + interrupt-names: > > + const: app > > + > > + msi-parent: true > > + > > + phys: > > + minItems: 1 > > + maxItems: 6 > > You have to define what each entry is. I assume this is 1 per lane > though I thought only a power of 2 number of lanes was valid. > In fact it is not 1 per lane, the PCIe accept lanes from the Comb PHY, and the phy can provide 1 lane or 2 lanes according to the PHY MUX. In detail, - PHY 0,1 is 2 lanes - PHY 2,3,4,5 is 1 lane. So the max number of the phys is 6 with 8 lanes. Maybe need a description link to the phy mux configuration? Regards, Inochi