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Fri, 26 Jun 2026 17:44:50 -0700 Date: Fri, 26 Jun 2026 17:44:49 -0700 From: Nicolin Chen To: Robin Murphy CC: , , , , , , , , , , , , , , , , Subject: Re: [PATCH v2 05/11] iommu/arm-smmu-v3: Submit CMDQ_OP_PRI_RESP for IOPF event Message-ID: References: <6c713c724fa09bf5a1b5e2247c633e516036f079.1779944354.git.nicolinc@nvidia.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF000015CB:EE_|DM4PR12MB7696:EE_ X-MS-Office365-Filtering-Correlation-Id: ec9b7f84-51ed-4f40-bb68-08ded3e54ef2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|30052699003|36860700016|82310400026|1800799024|23010399003|18002099003|22082099003|11063799006|5023799004|4143699003|56012099006|6133799003|3023799007; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: JEsBIbiYTe7fb+MRgEjVwj+lgWhJcSHjOujyz6x9t2Rn9TOswhKINxh6BWSmXfGRNVENmja3dJvfV14d6It6aCt17c0P3RLUBnaOojrfD0m0M2qgEhyiS1R6W8xbG2mOcdjkwO3oqHbUS11faAbyfMLUa6wlC9ar4nBHCSnTnr8rYQN6ZRxer5TdIrzl/w/p+eJDA+08teA6Z7Rlo/W83U9MzQGSPIyjiz7MEcmve2X3cRkHl4S1VJuJ2MnwcSD8GMwtLkXXOoK0thvdf/CGQ1Ao58qeOpg0oFfNT5fltZQydjS/vcOya/TMPG0szgBIIj0TxDKiGKVXScygHmC6ttRMIJAjAooLCKVvJjuNtuTvJD2ppm/L7NqYP0A4QEL8mAp85T2BkcbElWyjN9tsh9vcMyHTS/FpkyS7PIM73JL8YXBVzIArugQX9OGf5WW6 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Jun 2026 00:44:55.7432 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ec9b7f84-51ed-4f40-bb68-08ded3e54ef2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF000015CB.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB7696 On Fri, Jun 26, 2026 at 05:15:13PM +0100, Robin Murphy wrote: > On 28/05/2026 8:59 am, Nicolin Chen wrote: > > From: Malak Marrid > > > > To handle IOMMU_FAULT_PAGE_REQ from the PRI queue, arm_smmu_page_response() > > must issue a CMDQ_OP_PRI_RESP back to the SMMU. > > > > However, either a stall event in the EVTQ or a PRI request in the PRIQ can > > surface to the IOPF infrastructure with fault.type == IOMMU_FAULT_PAGE_REQ, > > and a single master can in principle be both stall-capable and PRI-capable > > No, the SMMU architecture does all it can to specifically forbid this, see > 3.12.1 and 16.4, it just can't be made architecturally ILLEGAL to enable > stalls for PCIe devices because there's no strict architectural definition > for what "a PCIe device" actually is. Similarly with the note in the > definition of STE.EATS about the relationship with CD.S - the unwritten > implication is that defining specific behaviours would only create an > unreasonable burden for hardware validation, for the sake of something that > nobody in their right mind should ever do anyway. > > The expectation is that RCiEPs which do speak stallable non-PCIe bus > protocols will not go to the effort of implementing ATS/PRI capabilities > (not least because there's every chance that such protocols simply doesn't > have that kind of transaction flow anyway). And conversely that it can be > considered an egregious firmware (or system design) error to even claim (let > alone force) stall capability for a real PCIe root port which may be > deadlocked by blocking its requirement for free-flowing writes. Thus I think > we could go so far as to refuse to handle any endpoint which did somehow > claim both. Oh, I missed that. This certainly can simplify things here. I will fix it. Thanks! Nicolin