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[34.142.255.199]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2c7444aad83sm105841775ad.79.2026.06.23.05.35.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jun 2026 05:35:27 -0700 (PDT) Date: Tue, 23 Jun 2026 12:35:19 +0000 From: Pranjal Shrivastava To: Matt Evans Cc: Alex Williamson , Jason Gunthorpe , "Tian, Kevin" , Leon Romanovsky , Alex Mastro , Christian =?iso-8859-1?Q?K=F6nig?= , Bjorn Helgaas , Logan Gunthorpe , Mahmoud Adam , David Matlack , =?iso-8859-1?Q?Bj=F6rn_T=F6pel?= , Sumit Semwal , Ankit Agrawal , Alistair Popple , "Kasireddy, Vivek" , "linux-kernel@vger.kernel.org" , "linux-media@vger.kernel.org" , "dri-devel@lists.freedesktop.org" , "linaro-mm-sig@lists.linaro.org" , "kvm@vger.kernel.org" , "linux-pci@vger.kernel.org" Subject: Re: [PATCH v3 6/9] vfio/pci: Clean up BAR zap and revocation Message-ID: References: <20260610154327.37758-7-matt@ozlabs.org> <24f34e59-7c3b-4b56-83bf-cb07e3f369a6@ozlabs.org> <20260619133116.GB278945@nvidia.com> <55ea7422-08d8-4c92-aa59-8ff6f9e9d781@ozlabs.org> <20260622171336.7d13f548@shazbot.org> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Tue, Jun 23, 2026 at 12:08:30PM +0100, Matt Evans wrote: > Hi Alex, > > On 23/06/2026 00:13, Alex Williamson wrote: > > On Fri, 19 Jun 2026 16:13:17 +0100 > > Matt Evans wrote: > > > >> Hi Jason, > >> > >> On 19/06/2026 14:31, Jason Gunthorpe wrote: > >>> On Thu, Jun 18, 2026 at 05:02:58PM +0100, Matt Evans wrote: > >>> > >>>> My understanding is that the sequences above wake a device that happens > >>>> to have previously been put into D3, and AFAICT it could only have got > >>>> there because of a previous vfio_pci_set_power_state(). Seems its only > >>>> caller is from the emulation of PCI_PM_CTRL using > >>>> vfio_lock_and_set_power_state(), and this zaps/revokes BAR access before > >>>> a transition to D3. Similarly, an attempt to access a BAR via an > >>>> ioctl/through vfio_pci_core_do_io_rw() fails the D3 check in > >>>> __vfio_pci_memory_enabled(), and besides will try to take the memory_lock. > >>> > >>> I thought the general design was the bars were made inaccessible > >>> before going to a low power state, and remain inaccessible while it is > >>> in low power? > >>> > >>> So the order of D0 doesn't matter. If it is not in D0 then there is no > >>> mappings and zap/revoke is a NOP. > >>> > >>> If is it in D0 then it doesn't matter because D0 is a nop. > >> Yes, that's what I'm getting at. :) If it's in D3 then BARs are > >> inaccessible, so as long as we go into D0 before the DMABUF move, the > >> order of the zap relative to the "go to D0" doesn't matter. > > > > I believe this is correct as well, but importantly we cannot assume > > that a stray read or write just returns -1 or gets dropped. This is > > exactly why we have such hard protections against the user accessing > > the device while it's disabled. Not all platforms, even within > > architectures that might otherwise be considered lenient of such > > accesses, consider this benign and might escalate to system level > > faults. > > We are in enthusiastic agreement here. > > > Let's be careful not to frame this as "the access doesn't matter > > anyway", the answer is instead that non-D0 devices already lack any > > mappings to access the device. Thanks, > > I agree that is not the right thing to say, for exactly that reason. > (For avoidance of any doubt, I didn't say that :) ) > > Thanks for confirming the behaviour. I hope Praan and Kevin are > satisfied that this patch doesn't cause the issues they first worried > about (the changed order of the zap relative to the D0 transition > doesn't have a detrimental effect because of the existing inaccessibility). > > Alex, I'll post v4 soon, but if you have any comments in the pipeline > please shout and I'll hold off awhile. I think the discussion addresses my concerns. I'm in agreement as well. Thanks, Praan