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Sat, 11 Jul 2026 22:44:17 -0700 (PDT) Received: from localhost ([2001:da8:7001:11::cb]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-38d11280409sm1900696a91.0.2026.07.11.22.44.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Jul 2026 22:44:17 -0700 (PDT) Date: Sun, 12 Jul 2026 13:43:33 +0800 From: Inochi Amaoto To: Alex Elder , Inochi Amaoto , Jingoo Han , Manivannan Sadhasivam , Bjorn Helgaas , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Yixun Lan , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Christian Bruel , Frank Li , Nam Cao , Qiang Yu , Krishna Chaitanya Chundru , Xincheng Zhang , Siddharth Vadapalli , Andy Shevchenko , Vidya Sagar , Neil Armstrong , Gustavo Pimentel Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, spacemit@lists.linux.dev, Yixun Lan , Longbin Li Subject: Re: [PATCH v4 5/6] dt-bindings: PCI: spacemit: Introduce Spacemit K3 PCIe host controller Message-ID: References: <20260709040027.958400-1-inochiama@gmail.com> <20260709040027.958400-6-inochiama@gmail.com> <58948c74-0990-449e-8eee-88cbb38db7e7@riscstar.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <58948c74-0990-449e-8eee-88cbb38db7e7@riscstar.com> On Fri, Jul 10, 2026 at 11:01:38AM -0500, Alex Elder wrote: > On 7/8/26 11:00 PM, Inochi Amaoto wrote: > > Add binding support for the PCIe controller on the SpacemiT K3 SoC. > > This controller is almost a standard Synopsys DesignWare PCIe IP, > > with some extra link and reset state control. > > > > Signed-off-by: Inochi Amaoto > > This looks OK to me. What I see is that K3 does not require > the interrupts and interrupt-names properties, allows up to > six PHYs (not just one), and adds a dbi2 register that is not > used by K1. > > I might have missed it, but I don't see where the dbi2 register > is used by the K3 code you have added. In pcie-designware.c, > I see that if no "dbi2" resource is found, memory at offset > 4096 from the "dbi" base is used. Does that apply for K3? > If so, maybe there's no need to define dbi2. > > -Alex > Weird, I have found the following logic in dw_pcie_get_resources() of pcie-designware.c ``` /* DBI2 is mainly useful for the endpoint controller */ if (!pci->dbi_base2) { res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2"); if (res) { pci->dbi_base2 = devm_pci_remap_cfg_resource(pci->dev, res); if (IS_ERR(pci->dbi_base2)) return PTR_ERR(pci->dbi_base2); } else { pci->dbi_base2 = pci->dbi_base + SZ_4K; } } ``` Regards, Inochi > > --- > > .../bindings/pci/spacemit,k1-pcie-host.yaml | 50 ++++++++++++++++--- > > 1 file changed, 43 insertions(+), 7 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml > > index c4c00b5fcdc0..54817d6fd9af 100644 > > --- a/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml > > +++ b/Documentation/devicetree/bindings/pci/spacemit,k1-pcie-host.yaml > > @@ -14,26 +14,29 @@ description: > > > PCIe IP. The controller uses the DesignWare built-in MSI interrupt > > controller, and supports 256 MSIs. > > -allOf: > > - - $ref: /schemas/pci/snps,dw-pcie.yaml# > > - > > properties: > > compatible: > > - const: spacemit,k1-pcie > > + enum: > > + - spacemit,k1-pcie > > + - spacemit,k3-pcie > > reg: > > + minItems: 4 > > items: > > - description: DesignWare PCIe registers > > - description: ATU address space > > - description: PCIe configuration space > > - description: Link control registers > > + - description: Data Bus Interface (DBI) shadow registers. > > reg-names: > > + minItems: 4 > > items: > > - const: dbi > > - const: atu > > - const: config > > - const: link > > + - const: dbi2 > > clocks: > > items: > > @@ -66,6 +69,8 @@ properties: > > interrupt-names: > > const: msi > > + msi-parent: true > > + > > spacemit,apmu: > > $ref: /schemas/types.yaml#/definitions/phandle-array > > description: > > @@ -84,7 +89,8 @@ patternProperties: > > properties: > > phys: > > - maxItems: 1 > > + minItems: 1 > > + maxItems: 6 > > vpcie3v3-supply: > > description: > > @@ -96,13 +102,43 @@ patternProperties: > > unevaluatedProperties: false > > +allOf: > > + - $ref: /schemas/pci/snps,dw-pcie.yaml# > > + - if: > > + properties: > > + compatible: > > + contains: > > + const: spacemit,k1-pcie > > + then: > > + properties: > > + reg: > > + maxItems: 4 > > + > > + reg-names: > > + maxItems: 4 > > + > > + patternProperties: > > + '^pcie@': > > + properties: > > + phys: > > + maxItems: 1 > > + > > + required: > > + - interrupts > > + - interrupt-names > > + else: > > + properties: > > + reg: > > + minItems: 5 > > + > > + reg-names: > > + minItems: 5 > > + > > required: > > - clocks > > - clock-names > > - resets > > - reset-names > > - - interrupts > > - - interrupt-names > > - spacemit,apmu > > unevaluatedProperties: false > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv