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[73.183.53.213]) by smtp.gmail.com with ESMTPSA id af79cd13be357-92ee5cf9d9bsm2074490485a.28.2026.07.16.11.48.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jul 2026 11:48:38 -0700 (PDT) Date: Thu, 16 Jul 2026 14:48:35 -0400 From: Brian Masney To: Christian Marangi Cc: Bjorn Helgaas , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ryder Lee , Michael Turquette , Stephen Boyd , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Jianjun Wang , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v4 2/4] clk: en7523: add support for dedicated PCIe PERSTOUT reset Message-ID: References: <20260714115848.8537-1-ansuelsmth@gmail.com> <20260714115848.8537-3-ansuelsmth@gmail.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260714115848.8537-3-ansuelsmth@gmail.com> User-Agent: Mutt/2.4.0 (2026-06-19) Hi Christian, On Tue, Jul 14, 2026 at 01:58:44PM +0200, Christian Marangi wrote: > Add support for resetting the PCIe lines with the PERSTOUT reset. These > special reset are controlled by the PCIC register and are specific to each > of the 3 PCIe lines. > > Notice that reset logic is inverted for these bit where 0 is assert and 1 > deassert. This is intenrally handled in the reset function. s/intenrally/internally/ The "these bit" above is awkward as well. Sorry I don't have a suggestion offhand, but I see what you mean below based on the code. > > PCI enable/disable are updated to drop PERSTOUT bits in favor dedicated > reset handling. > > Signed-off-by: Christian Marangi > --- > drivers/clk/clk-en7523.c | 39 ++++++++++++++++++++++++++++----------- > 1 file changed, 28 insertions(+), 11 deletions(-) > > diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c > index 1ab0e2eca5d3..c9b21d9bf2f3 100644 > --- a/drivers/clk/clk-en7523.c > +++ b/drivers/clk/clk-en7523.c > @@ -338,6 +338,7 @@ static const struct en_clk_desc en7581_base_clks[] = { > static const u16 en7581_rst_ofs[] = { > REG_RST_CTRL2, > REG_RST_CTRL1, > + REG_NP_SCU_PCIC, > }; > > static const u16 en751221_rst_ofs[] = { > @@ -450,6 +451,11 @@ static const u16 en7581_rst_map[] = { > [EN7581_CPU_TIMER_RST] = RST_NR_PER_BANK + 28, > [EN7581_PCIE_HB_RST] = RST_NR_PER_BANK + 29, > [EN7581_XPON_MAC_RST] = RST_NR_PER_BANK + 31, > + > + /* RST_PCIC */ > + [EN7581_PCIC_PERSTOUT0_RST] = 2 * RST_NR_PER_BANK + 29, > + [EN7581_PCIC_PERSTOUT1_RST] = 2 * RST_NR_PER_BANK + 26, > + [EN7581_PCIC_PERSTOUT2_RST] = 2 * RST_NR_PER_BANK + 16, > }; > > static const u16 en751221_rst_map[] = { > @@ -635,9 +641,7 @@ static int en7581_pci_enable(struct clk_hw *hw) > void __iomem *np_base = cg->base; > u32 val, mask; > > - mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1 | > - REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT2 | > - REG_PCI_CONTROL_PERSTOUT; > + mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1; > val = readl(np_base + REG_PCI_CONTROL); > writel(val | mask, np_base + REG_PCI_CONTROL); > > @@ -650,9 +654,7 @@ static void en7581_pci_disable(struct clk_hw *hw) > void __iomem *np_base = cg->base; > u32 val, mask; > > - mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1 | > - REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT2 | > - REG_PCI_CONTROL_PERSTOUT; > + mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1; > val = readl(np_base + REG_PCI_CONTROL); > writel(val & ~mask, np_base + REG_PCI_CONTROL); > usleep_range(1000, 2000); > @@ -754,14 +756,21 @@ static int en7523_reset_update(struct reset_controller_dev *rcdev, > unsigned long id, bool assert) > { > struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev); > - void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK]; > + u32 offset = rst_data->bank_ofs[id / RST_NR_PER_BANK]; > + void __iomem *addr = rst_data->base + offset; > + bool inverted = false; > u32 val; > > + /* For PCIC reset logic is inverted, 0:assert 1:deassert*/ Add space before end of comment. > + if (offset == REG_NP_SCU_PCIC) > + inverted = true; > + > val = readl(addr); > + val &= ~BIT(id % RST_NR_PER_BANK); > if (assert) > - val |= BIT(id % RST_NR_PER_BANK); > + val |= inverted ? 0 : BIT(id % RST_NR_PER_BANK); > else > - val &= ~BIT(id % RST_NR_PER_BANK); > + val |= inverted ? BIT(id % RST_NR_PER_BANK) : 0; Could you do: if (assert ^ inverted) Then keep the existing logic for val inside the if/else? > writel(val, addr); > > return 0; > @@ -783,9 +792,17 @@ static int en7523_reset_status(struct reset_controller_dev *rcdev, > unsigned long id) > { > struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev); > - void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK]; > + u32 offset = rst_data->bank_ofs[id / RST_NR_PER_BANK]; > + void __iomem *addr = rst_data->base + offset; > + bool inverted = false; > + u32 val; > + > + /* For PCIC reset logic is inverted, 0:assert 1:deassert*/ Add space before */ Brian