From: Lukas Wunner <lukas@wunner.de>
To: peng.guo@montage-tech.com
Cc: linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, bhelgaas@google.com,
dave@stgolabs.net, jic23@kernel.org, dave.jiang@intel.com,
alison.schofield@intel.com, vishal.l.verma@intel.com,
ira.weiny@intel.com, djbw@kernel.org, johnny.li@montage-tech.com,
jingzhong.yang@montage-tech.com, engguopeng@buaa.edu.cn
Subject: Re: [PATCH 1/2] PCI: Add MMIO Capabilities Register Block definitions
Date: Sun, 16 Aug 2026 13:19:48 +0200 [thread overview]
Message-ID: <aoGc1Ie-S5-Ytsp_@wunner.de> (raw)
In-Reply-To: <20260816084957.3316727-2-peng.guo@montage-tech.com>
On Sun, Aug 16, 2026 at 04:49:56PM +0800, peng.guo@montage-tech.com wrote:
> The PCIe Management Message Passthrough via MMIO Mailbox ECN defines
> the MMIO Capabilities Register Block (MCAP). MCAP contains an array
> header followed by capability headers that describe the ID, version,
> location, size, and vendor of each MMIO capability.
That ECN went into PCIe r6.2. For ECNs that are already part of the
PCIe Base Spec, it's better to cite the section in the latest spec
revision, i.e. PCIe r7.0 sec 6.35, rather than the ECN that originally
introduced the feature. Reviewers (like me) generally have the latest
spec revision at hand, but not every ECN.
Otherwise this is
Reviewed-by: Lukas Wunner <lukas@wunner.de>
next prev parent reply other threads:[~2026-08-16 11:19 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-16 8:49 [PATCH 0/2] PCI/CXL: Distinguish CXL capabilities in MCAP peng.guo
2026-08-16 8:49 ` [PATCH 1/2] PCI: Add MMIO Capabilities Register Block definitions peng.guo
2026-08-16 9:15 ` sashiko-bot
2026-08-16 11:19 ` Lukas Wunner [this message]
2026-08-16 8:49 ` [PATCH 2/2] cxl/core: Skip non-CXL capabilities in MCAP peng.guo
2026-08-16 9:19 ` sashiko-bot
2026-08-16 11:22 ` Lukas Wunner
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