On Thu, Aug 27, 2026 at 12:03:58PM -0500, Bjorn Helgaas wrote:
> On Thu, Aug 27, 2026 at 05:39:19PM +0800, Linmao Li wrote:
> > The PCI Express Link Capabilities and Link Status registers are at offsets
> > 0x0c and 0x12 from the capability header, respectively.  Since the driver
> > uses 0x5a for Link Status, Link Capabilities starts at 0x54, not 0x56.
> > 
> > Reading a 16-bit value at 0x56 returns the upper half of the Link
> > Capabilities register.  When a hotplug-capable port has no link during
> > probe, tegra264_pcie_icc_set() consequently derives the maximum speed and
> > width from unrelated bits and requests the wrong interconnect bandwidth.
> > 
> > Use the correct Link Capabilities offset.
> > 
> > Fixes: 01c3c27a0ef6 ("PCI: tegra264: Add Tegra264 support")
> > Signed-off-by: Linmao Li <lilinmao@kylinos.cn>
> > ---
> >  drivers/pci/controller/pcie-tegra264.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/pci/controller/pcie-tegra264.c b/drivers/pci/controller/pcie-tegra264.c
> > index 653136db401e0..3a672d18c4d2d 100644
> > --- a/drivers/pci/controller/pcie-tegra264.c
> > +++ b/drivers/pci/controller/pcie-tegra264.c
> > @@ -49,7 +49,7 @@
> >  #define XAL_RC_BAR_CNTL_STANDARD_64B_BAR_EN	BIT(2)
> >  
> >  /* XTL registers */
> > -#define XTL_RC_PCIE_CFG_LINK_CAPS		0x56
> > +#define XTL_RC_PCIE_CFG_LINK_CAPS		0x54
> >  #define XTL_RC_PCIE_CFG_LINK_STATUS		0x5a
> 
> If this is a standard PCIe Capability, and since we use the standard
> #defines like PCI_EXP_LNKSTA_CLS and PCI_EXP_LNKCAP_SLS for values
> read from it, it appears to be, I think these XTL_RC* #defines should
> somehow be based on the existing PCI_EXP_LNKSTA and PCI_EXP_LNKCAP.
> 
> E.g., we could read from pcie->ecam + XTL_RC_PCIE_CAP + PCI_EXP_LNKSTA.
> That way grep would be more useful.

That's a good point. And, yes, this does look like a regular PCIe
capability, so I'll try to rework this using the standard defines.

Thierry