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Fri, 4 Sep 2026 22:08:31 -0700 Received: from nvidia.com (10.127.8.11) by mail.nvidia.com (10.126.190.180) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.46 via Frontend Transport; Fri, 4 Sep 2026 22:08:25 -0700 Date: Fri, 4 Sep 2026 22:08:24 -0700 From: Nicolin Chen To: Jonathan Cameron CC: , , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v3 09/13] iommu/arm-smmu-v3: Support PRI Page Request in arm_smmu_handle_ppr() Message-ID: References: <0fe5f381aae307045e4cab97f8000c575f34a9ee.1788222486.git.nicolinc@nvidia.com> <178846311318.1308030.15663048615954357081.b4-review@b4> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <178846311318.1308030.15663048615954357081.b4-review@b4> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF000061C7:EE_|DS0PR12MB8341:EE_ X-MS-Office365-Filtering-Correlation-Id: 3560613f-abf9-44ca-696d-08df0b0bc380 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|23010399003|36860700016|1800799024|82310400026|4143699003|5023799004|10067099003|11063799006|22082099003|18002099003|56012099006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 4jv8fMZx9tmjaXWq5kZp9FPPrJg4h4FLAbzDrNhTIE05E12l5UykOCzE2C/TDCBABR07gnvR2Yr/HRbKnDwx0WeRLJ8P/YYH8z2BmG/fNyz6y0U5Y/RLO3IsAxQFCmPHleXuiz/XzDZlK6f7+cZHGyRgB2GIetufokI8ieNp2OhEmt9bJBpCrfhx3J+JrB6CgLlWCG4E2HMsvxfw0F7WJqGY/v6HLSTOfuSNPTq3bpj/2+214aMUaJMD/e6mJ7JNW0BIS69OXbSHCKv3rjH1mVryQcNmQLeKG5A1mUCflaCCFZrGbabFXHeaSNT5yNeten8izOjthhLCKAqGLxE9wePYcJhl8/HE72ltj9JadJFdMD3FEZARUtNM4peU1vrxnCAm+63NKLEVKGxlSdgiQc+HNfRTWDOUr0EStueVUDRyziaF/o3diKSylTiO5Ba9 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Sep 2026 05:08:46.0971 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3560613f-abf9-44ca-696d-08df0b0bc380 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF000061C7.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8341 On Thu, Sep 03, 2026 at 12:18:33PM -0700, Jonathan Cameron wrote: > > For an unrecognised StreamID or a master without master->pri_enabled, fall > > through to the existing "unexpected PRI request" log + LAST-page DENY path > > to release the credit per the PCIe PRI spec. Merge its two info prints in > > Either don't bother mentioning pcie spec explicitly or expand that > to a useful reference - so section number, section title. Dropped: For an unrecognised StreamID or a master without master->pri_enabled, fall through to the existing "unexpected PRI request" log + LAST-page DENY path. Merge its two info prints in the path into one single ratelimited line, as a malfunctioning device can spam unrecognised requests that will flood the kernel log. > > On PRIQ overflow, partial requests stored via report_partial_fault() whose > > LAST-page entry was lost stay in iopf_param->partial. Drop them by calling > > iopf_queue_discard_partial(), matching intel-iommu's handling. Do it after > > the queue is fully drained, since the visible entries all precede the loss > > point: a group whose LAST-page entry is still in the queue gets assembled > > before the discard, rather than losing its stored partials to it. Nor can > > a new arrival race against the discard, since an active overflow inhibits > > new entries from being written to the PRI queue (IHI0070 8.1), up until a > > final CONS write acknowledges it. > > Kind of a general comment. I'm guessing AI assisted heavily in these. > Whilst I haven't found much that definitely doesn't belong in a patch > description, they do end up rather more verbose than ideal. Maybe > poke it to be more terse in English language choices at least? Well, some of the paragraphs in the commit messages turned out to be indeed verbose, compared to my original writings. One of the reasons was to justify against Sashiko that often nitpicks on a corner case, (which surprisingly works well). I broke it into parts; hope this might ease a bit: On PRIQ overflow, partial requests stored via report_partial_fault() whose LAST-page entry was lost stay in iopf_param->partial. Drop them by calling iopf_queue_discard_partial(), matching intel-iommu's handling. Do it only after the queue is fully drained, since the visible entries all precede the loss point: a group whose LAST-page entry is still in the queue gets assembled before the discard, rather than losing its stored partials to it. Nothing can arrive in between, as an active overflow inhibits new entries from being written to the PRI queue until a final CONS write acknowledges it (IHI0070 8.1). Thanks Nicolin