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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3339ac24d7esm77752519eec.15.2026.09.09.23.43.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Sep 2026 23:43:52 -0700 (PDT) Date: Thu, 10 Sep 2026 14:43:45 +0800 From: Shawn Guo To: Krishna Chaitanya Chundru Cc: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Bjorn Andersson , Maxime Chevallier , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org Subject: Re: [PATCH v3 1/5] dt-bindings: phy: qcom: add Nord QMP PCIe PHY binding Message-ID: References: <20260909-nord-v3-0-b0a82721c547@oss.qualcomm.com> <20260909-nord-v3-1-b0a82721c547@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20260909-nord-v3-1-b0a82721c547@oss.qualcomm.com> X-Authority-Analysis: v=2.4 cv=YZYodARf c=1 sm=1 tr=0 ts=6aa251aa cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=Tb11Ti1d2fZyuSkRe-0A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=_Vgx9l1VpLgwpw_dHYaR:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTEwMDA3MCBTYWx0ZWRfX0QTh3GuGgVM8 Smn9IG9+0sFaMiu3xjiuS3ixhgUSjqOppKiF9XMz1VLBhizfN/oLu0nJ+dybVXs57stivpqqy+g mfV8oiqXlf4N0Z7yJo3W5WDZUegT5Tw= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTEwMDA3MCBTYWx0ZWRfXxZ5BmN0689gu g39o8Q2A0Y6T6KWuEQcFJywWq/mX7CugGaE5rJISrlnJvK9UwWXxj7w73bkGV5blogMJK11WOP1 rIQOOM8CrWflROB7AtAP6/rtSWRl1wGK17SjAMBUCQdfEl0WMctFvViDurgbHtrdvObZ+OfoUMu HWR5A5Td+f4LxV0Tq181ev2+xb0Qo9UMk9fvINslVPubq7bJf4kLND5d00QPtWlus16NIfEoBHu /C/4QyCC6BJPgpJZK44/scV1iYFKZmAu4BHocDJKWVoIDZOyWZAI4XopkGuTtbHRu/K2HtBF9Yi 3etTI3rPV2+R4ER8Rya+krII2jU738gQd49D2o3xStstOoZuroa0ofnYBpBLFUQrl9ihz/YaGxx XazIKBihyuGMV/V66BsbNT1wA0dAhzgUrrtk+0WCpUSUhucZXuxVAXuKTjCf7pL4JjswWZNJvWe /PEo4ulri1xtfMHCsKw== X-Proofpoint-GUID: gM2CKyNZgRvj00_WZgUP-qdIoMOgCmju X-Proofpoint-ORIG-GUID: gM2CKyNZgRvj00_WZgUP-qdIoMOgCmju X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-10_02,2026-09-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 impostorscore=0 adultscore=0 bulkscore=0 phishscore=0 spamscore=0 clxscore=1015 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609100070 On Wed, Sep 09, 2026 at 05:18:16PM +0530, Krishna Chaitanya Chundru wrote: > Document the PCIe PHY found on the Qualcomm Nord platform. > > Nord has a Gen5-capable QMP PCIe PHY that can operate in multiple > lane configurations using four PHY segments (A/B/C/D). The active > topology is selected by firmware through a TCSR configuration > register and may be configured as x16, x8+x8, x8+x4+x4, or > x8+x4+x2+x2. > > The binding describes the register regions, clocks, resets, power > domains, regulators, PHY provider interface, clock provider interface, > and the qcom,link-mode property used by the driver to discover the > active lane configuration programmed by firmware. > > Signed-off-by: Krishna Chaitanya Chundru > --- > .../phy/qcom,nord-qmp-gen5x16-pcie-phy.yaml | 272 +++++++++++++++++++++ > 1 file changed, 272 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/qcom,nord-qmp-gen5x16-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,nord-qmp-gen5x16-pcie-phy.yaml > new file mode 100644 > index 000000000000..624ad7e7d13e > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/qcom,nord-qmp-gen5x16-pcie-phy.yaml > @@ -0,0 +1,272 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/qcom,nord-qmp-gen5x16-pcie-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm Nord QMP Quadfurcated PCIe multiple link-mode PHY > + > +maintainers: > + - Krishna Chaitanya Chundru > + > +description: | Can we drop "|" like below? @@ -9,7 +9,7 @@ title: Qualcomm Nord QMP Quadfurcated PCIe multiple link-mode PHY maintainers: - Krishna Chaitanya Chundru -description: | +description: The Qualcomm Nord PCIe PHY is a Gen5-capable QMP PCIe PHY composed of four PHY ports (A/B/C/D). The ports can be combined to support multiple lane topologies, including x16, x8+x8, x8+x4+x4 and @@ -101,7 +101,7 @@ properties: vdda-pll-d-supply: true qcom,link-mode: - description: | + description: Reference to the TCSR syscon and the offset of the TCSR_PCIE_LINK_CONFIG_MODE register. 0 (QMP_PCIE_NORD_MODE_X16) — all ports ganged as x16 @@ -129,8 +129,8 @@ properties: "#phy-cells": const: 1 - description: | - Selects the PHY instance by index: + description: + Selects the PHY instance by index. 0 — port A (up to Gen5 x8; anchor in x16 mode) 1 — port B (up to Gen5 x4) 2 — port C (up to Gen5 x2) Shawn