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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-144f294d894sm5341693c88.2.2026.09.22.01.14.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Sep 2026 01:14:05 -0700 (PDT) Date: Tue, 22 Sep 2026 16:13:57 +0800 From: Shawn Guo To: Krishna Chaitanya Chundru Cc: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Manivannan Sadhasivam , Bjorn Helgaas , Bjorn Andersson , Maxime Chevallier , Philipp Zabel , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, Krzysztof Kozlowski , Konrad Dybcio , Qiang Yu , Manivannan Sadhasivam Subject: Re: [PATCH v4 0/6] Add PCIe support for Qualcomm Nord platform Message-ID: References: <20260921-nord-v4-0-ed05c6e09240@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20260921-nord-v4-0-ed05c6e09240@oss.qualcomm.com> X-Proofpoint-Spam-Info: AW1haW4tMjYwOTIyMDExOCBTYWx0ZWRfX0F7TlMFvvhzU o/nh2KM3ztKlemIInMnw3B3/OUjsJtRppuCQv9iDrBepTRHsn2YcYLh2KtuWVaq6A6lU2AN3Sc2 P2y5BALz+mIK7k+GHK+O/eRdC3vAUpE= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTIyMDExOCBTYWx0ZWRfX0ARgteLCylRy eUuO5WFTLQCbhZGWU/j+vvvVW+LAGRr8TOAar2courFiUWpFjyIe3wZrOP7XN6I09AU4MnrioPY v+T5Bp86xHdbWWEA/HX8sk0LUfLD5ydqZ06amevR4bsqUGWPcQjneuVdxt3Lmx+v7ru8UonBNdu MLiZVYdOUsZda6yKyLGvVo9N06CYISvUvj4jzBD9XFymveZIaoHC2/XzrLSrsadQA56zXaN4W4g U7ezPGnrg704sWqX+xuYJRJOeAHA4W2exmctTEvATuIbeny9CpDhRRPNKn/PV2o7VtcY3h1x9tj sL2Rm85xqRDBtVSFqu5pKseZM13NHzAP4zRMEnA+RMCAzk+38CvTGEZkpojfySInxtbAHWgomC/ OjgyAbYr0lwMNONbOM+pFm7agw8LEJleZ4tse2uVB9HXyBR1mteInM6ZioNMFLdte0RHBQo95rP yD8gWgsMDMD8m5qLV+w== X-Authority-Analysis: v=2.4 cv=E8FYNqdl c=1 sm=1 tr=0 ts=6ab238d0 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=bC-a23v3AAAA:8 a=EUspDBNiAAAA:8 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=1XWaLZrsAAAA:8 a=P-IC7800AAAA:8 a=JfrnYn6hAAAA:8 a=Arp2LTHWbRu_ztUwPq4A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 a=FO4_E8m0qiDe52t0p3_H:22 a=cvBusfyB2V15izCimMoJ:22 a=d3PnA9EDa4IxuAV0gXij:22 a=1CNFftbPRP8L7MoqJWF3:22 X-Proofpoint-ORIG-GUID: c7iLddIO0pBYLfF9FjP1yrLNEefPlQg0 X-Proofpoint-GUID: c7iLddIO0pBYLfF9FjP1yrLNEefPlQg0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-21_07,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 spamscore=0 lowpriorityscore=0 impostorscore=0 phishscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609220118 On Mon, Sep 21, 2026 at 11:07:08AM +0530, Krishna Chaitanya Chundru wrote: > This series adds PCIe support for the Qualcomm Nord (SA8797P) platform. > > Nord has a single Gen5-capable QMP PCIe PHY block split into four > independently-clocked and independently-resettable ports (A/B/C/D). > Firmware selects the active lane topology at boot via a TCSR > configuration register, and the same PHY block can appear as a single > x16 port, x8+x8, x8+x4+x4, or x8+x4+x2+x2 depending on that mode. This > is similar in spirit to the Glymur multi-PHY support already posted, > except Nord's PHY registers are programmed by Linux rather than by > firmware, so this series adds the PLL, TXRXZ, PCS and PCS-lane init > tables along with the power-up/power-down/soft-reset sequencing needed > to bring each port up. > > The series also documents and wires up the qcom,nord-pcie compatible > (reusing the existing SA8775P PCIe controller binding), and adds a > CORE_CLK_CGC_DIS/AUX_PWR_DET workaround required to avoid a timing > convergence issue in the PCIe power domain. > > Signed-off-by: Krishna Chaitanya Chundru > --- > To: Vinod Koul > To: Neil Armstrong > To: Rob Herring > To: Krzysztof Kozlowski > To: Conor Dooley > To: Chaitanya Chundru > To: Lorenzo Pieralisi > To: Krzysztof Wilczyński > To: Manivannan Sadhasivam > To: Bjorn Helgaas > To: Bjorn Andersson > To: Maxime Chevallier > To: Philipp Zabel > Cc: shengchao.guo@oss.qualcomm.com > Cc: linux-arm-msm@vger.kernel.org > Cc: linux-phy@lists.infradead.org > Cc: devicetree@vger.kernel.org > Cc: linux-kernel@vger.kernel.org > Cc: linux-pci@vger.kernel.org > Cc: shengchao.guo@oss.qualcomm.com > > --- > Changes in v4: > - Couple of nits in dt binding & phy driver (shawn, Mani) > - Add proper description for link-mode & phy-cells > - Remove soc node and address cells from example (Mani) > - change cgc_dis_workaround to disable_cgc (Mani) > - Split common changes and nord changes (Mani) > - Link to v3: https://patch.msgid.link/20260909-nord-v3-0-b0a82721c547@oss.qualcomm.com > > Changes in v3: > - change the name to quadfurcated phy (Konrad). > - remove min items and change clocks order (Krzysztof). > - Factor out the common config and create overlays & try to use common > symbols for glymur and nord (Konrad). > - create qphy_setbit and qphy_clrbit (Qiang Yu). > - and in qmp_pcie_exit() apply settings only when nocsr is present (Qiang Yu). > - Link to v2: https://patch.msgid.link/20260828-nord-v2-0-18bf59d19d6f@oss.qualcomm.com > > Changes in v2: > - Fix dtbinding errors (Krzysztof) > - Link to v1: https://patch.msgid.link/20260825-nord-v1-0-7c02f2b8765a@oss.qualcomm.com > > --- > Krishna Chaitanya Chundru (6): > dt-bindings: phy: qcom: add Nord QMP PCIe PHY binding > dt-bindings: pci: qcom: add Nord PCIe controller compatible > PCI: qcom: Add Nord PCIe controller support > phy: qcom: qmp: Move qphy_setbits/clrbits/checkbits to common header > phy: qcom: qmp-pcie: Refactor common multiphy handling > phy: qcom: qmp-pcie: Add Nord Gen5x16 PCIe multi-PHY support On Nord platform: Tested-by: Shawn Guo