Linux PCI subsystem development
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From: Lorenzo Bianconi <lorenzo.bianconi@oss.qualcomm.com>
To: Bjorn Helgaas <helgaas@kernel.org>
Cc: "Alex Elder" <elder@riscstar.com>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Chaitanya Chundru" <krishna.chundru@oss.qualcomm.com>,
	"Linus Walleij" <linusw@kernel.org>,
	"Bartosz Golaszewski" <brgl@kernel.org>,
	"Bjorn Andersson" <andersson@kernel.org>,
	"Konrad Dybcio" <konradybcio@kernel.org>,
	"Michael Walle" <mwalle@kernel.org>,
	"Daniel Thompson" <daniel@riscstar.com>,
	"Sushrut Shree Trivedi" <sushrut.trivedi@oss.qualcomm.com>,
	linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-gpio@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	"Bartosz Golaszewski" <bartosz.golaszewski@oss.qualcomm.com>,
	"Manivannan Sadhasivam" <manivannan.sadhasivam@oss.qualcomm.com>
Subject: Re: [PATCH v5 2/5] gpio: tc9563: Add support for the embedded GPIO controller
Date: Wed, 23 Sep 2026 22:29:12 +0200	[thread overview]
Message-ID: <arQ2mDjqHv4gmoOK@lore-desk> (raw)
In-Reply-To: <20260923200255.GA1934030@bhelgaas>

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> On Wed, Sep 23, 2026 at 01:59:49PM -0500, Alex Elder wrote:
> > On 9/23/26 1:52 PM, Bjorn Helgaas wrote:
> > > Patch [1/5] and a comment below mention 37 GPIOs, this mentions 35.
> > > Are they supposed to match?  Maybe 35 doesn't include the two reserved
> > > ones?
> > 
> > They are numbered 0..36, and two of them (20 and 21) are reserved.
> 
> That's what I suspected.  Any suggestions for rewording this to remove
> the ambiguity?  The current "providing 37 GPIO lines" and "implements
> 35 GPIOs" just raises the question.

what about something like:

"
Add a driver for the GPIO controller embedded in the Toshiba TC9563
PCIe switch (and the Qualcomm QPS615). The device implements 37 GPIOs
using two register banks: three registers control the first 32 GPIOs
and three more control GPIOs 32-36. GPIOs 20 and 21 are reserved while
GPIOs 22-24, 27-28, 31, and 34 are input-only.
"

Regards,
Lorenzo

> 
> > Of those, 10 (numbers 0-6, 12, 35, and 36) exposed outside the
> > TC9564 chip itself.

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  reply	other threads:[~2026-09-23 20:29 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-09 14:55 [PATCH v5 0/5] PCI/pwrctrl: tc9563: Introduce support for embedded GPIO controller Lorenzo Bianconi
2026-09-09 14:55 ` [PATCH v5 1/5] dt-bindings: PCI: toshiba,tc9563: Document " Lorenzo Bianconi
2026-09-09 15:04   ` sashiko-bot
2026-09-09 15:38     ` Lorenzo Bianconi
2026-09-11  7:29   ` Krzysztof Kozlowski
2026-09-09 14:55 ` [PATCH v5 2/5] gpio: tc9563: Add support for the " Lorenzo Bianconi
2026-09-09 15:06   ` sashiko-bot
2026-09-22 16:18   ` Manivannan Sadhasivam
2026-09-22 20:06     ` Linus Walleij
2026-09-23 14:44     ` Bartosz Golaszewski
2026-09-23 18:52   ` Bjorn Helgaas
2026-09-23 18:59     ` Alex Elder
2026-09-23 20:02       ` Bjorn Helgaas
2026-09-23 20:29         ` Lorenzo Bianconi [this message]
2026-09-09 14:55 ` [PATCH v5 3/5] PCI/pwrctrl: tc9563: Add GPIO auxiliary device support Lorenzo Bianconi
2026-09-09 15:15   ` sashiko-bot
2026-09-09 15:42     ` Lorenzo Bianconi
2026-09-09 14:55 ` [PATCH v5 4/5] PCI/pwrctrl: tc9563: Switch per-port reset to GPIO descriptor API Lorenzo Bianconi
2026-09-09 15:05   ` sashiko-bot
2026-09-09 14:55 ` [PATCH v5 5/5] arm64: dts: qcom: qcs6490-rb3gen2: Enable TC9563 embedded GPIO controller Lorenzo Bianconi
2026-09-09 15:05   ` sashiko-bot
2026-09-22 16:16   ` Manivannan Sadhasivam
2026-09-23 20:43 ` [PATCH v5 0/5] PCI/pwrctrl: tc9563: Introduce support for " Bjorn Helgaas
2026-10-02 17:54   ` Bjorn Helgaas
2026-10-02 19:18     ` Alex Elder

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