Re: [PATCH v9 0/7] VMD add second root bus support

[Manivannan Sadhasivam <mani@kernel.org>]

On Mon, Oct 26, 2026 at 08:54:53PM +0000, Szymon Durawa wrote:
> This series adds support for a second VMD root bus.
> 
> Today the VMD driver can enumerate and manage devices only behind the
> first VMD root bus. Starting with Intel Arrow Lake, VMD may expose a
> second root bus (BUS1), and devices behind that bus are not discovered
> by the current driver.
> 
> The hardware model for Intel Arrow Lake VMD is slightly different
> from earlier VMD generations:
> 
> - CFGBAR, MEMBAR1, and MEMBAR2 are shared by both VMD root buses.
> - Root ports on BUS1 have PCI_PRIMARY_BUS hardwired to 0x80.
> - Interrupt handling remains based on the existing VMD MSI/MSI-X and
>   irq_domain model; this series does not introduce a separate interrupt
>   domain for BUS1.
> 
> To support that layout, the series first refactors the current code so
> resource setup, bus creation, and enumeration are split into helpers.
> It then partitions the shared CFGBAR/MEMBAR apertures between BUS0 and
> BUS1 and creates a second root bus in its own emulated PCI domain.
> Reads of PCI_PRIMARY_BUS from BUS1 root port bridges are emulated to
> return the actual root bus number, so PCI core bridge scanning does not
> detect a mismatch and lose BUS1 subordinate device discovery. This
> replaces the separate workaround patch used in v8.
> 
> Patch overview:
> 
> - Patches 1-4 extract helper functions for bus enumeration, CFGBAR and
>   MEMBAR configuration, and root-bus creation.
> - Patch 5 replaces hardcoded resource indices and constants with enums
>   and defines.
> - Patch 6 converts single-bus state (bus, busn_start, sysdata) into
>   per-root-bus arrays.
> - Patch 7 adds BUS1 resource partitioning, a separate PCI domain for
>   BUS1, PCI_PRIMARY_BUS read emulation for BUS1 root ports, and
>   second-root-bus support.
> 
> Tested on an Arrow Lake platform with NVMe devices present behind both
> VMD root buses. With the series applied, devices behind BUS0 and BUS1
> are enumerated and become visible to the kernel.
> 

Series doesn't apply on top of v7.4-rc1. Please rebase and resend.

- Mani

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