Re: [PATCH 1/7] PCI/DPC: Avoid access to non-existent AER capability

[Lukas Wunner <lukas@wunner.de>]

On Tue, Sep 29, 2026 at 11:49:40AM -0700, Kuppuswamy Sathyanarayanan wrote:
> On 9/27/2026 11:02 AM, Lukas Wunner wrote:
> > Downstream Port Containment does not mandate presence of an Advanced Error
> > Reporting capability, so a Downstream Port may support DPC, but not AER
> > (PCIe r7.1 sec 6.2.11.2).
[...]
> > - dpc_get_aer_uncorrect_severity() uses it to discern whether a Fatal or
> >   Non-Fatal Error triggered DPC.  Access the Device Status Register
> >   instead, in accordance with PCIe r7.1 sec 6.2.5.
> 
> This changes behavior not only for AER-incapable ports, but also for
> the AER-capable ones.  PCIe r7.1 sec 7.5.3.5 says for the Fatal/
> Non-Fatal Error Detected bits:
> 
>   "For Functions supporting Advanced Error Handling, errors are logged
>    in this register regardless of the settings of the Uncorrectable
>    Error Mask register."
> 
> The old code only considered unmasked errors, the new code also picks
> up masked ones.  So a masked Fatal error (e.g. Surprise Down) alongside
> the unmasked Non-Fatal error which triggered DPC is now reported as
> Fatal.  Stale bits from earlier masked errors can have the same effect.
> 
> Since this is tagged for stable, how about keeping the AER-based logic
> when dev->aer_cap is present and using DEVSTA only as a fallback?

An excellent observation, I've changed it as you've suggested.
Thanks for the thoughtful review!

Lukas