From: neil.armstrong@linaro.org
To: Geraldo Nascimento <geraldogabriel@gmail.com>,
linux-rockchip@lists.infradead.org
Cc: "Shawn Lin" <shawn.lin@rock-chips.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Heiko Stuebner" <heiko@sntech.de>,
"Vinod Koul" <vkoul@kernel.org>,
"Kishon Vijay Abraham I" <kishon@kernel.org>,
"Rick wertenbroek" <rick.wertenbroek@gmail.com>,
linux-phy@lists.infradead.org, linux-pci@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v7 4/4] phy: rockchip-pcie: Properly disable TEST_WRITE strobe signal
Date: Mon, 30 Jun 2025 10:49:25 +0200 [thread overview]
Message-ID: <b3130adb-87e8-4c24-8267-0d5e53e363e8@linaro.org> (raw)
In-Reply-To: <60ad1985a0de0a6b47044ea9c0acefe6ff865aad.1751200382.git.geraldogabriel@gmail.com>
On 29/06/2025 14:48, Geraldo Nascimento wrote:
> pcie_conf is used to touch TEST_WRITE strobe signal. This signal should
> be enabled, a little time waited, and then disabled. Current code clearly
> was copy-pasted and never disables the strobe signal. Adjust the define.
> While at it, remove PHY_CFG_RD_MASK which has been unused since
> 64cdc0360811 ("phy: rockchip-pcie: remove unused phy_rd_cfg function").
>
> Signed-off-by: Geraldo Nascimento <geraldogabriel@gmail.com>
> ---
> drivers/phy/rockchip/phy-rockchip-pcie.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchip/phy-rockchip-pcie.c
> index f22ffb41cdc2..4e2dfd01adf2 100644
> --- a/drivers/phy/rockchip/phy-rockchip-pcie.c
> +++ b/drivers/phy/rockchip/phy-rockchip-pcie.c
> @@ -30,9 +30,8 @@
> #define PHY_CFG_ADDR_SHIFT 1
> #define PHY_CFG_DATA_MASK 0xf
> #define PHY_CFG_ADDR_MASK 0x3f
> -#define PHY_CFG_RD_MASK 0x3ff
> #define PHY_CFG_WR_ENABLE 1
> -#define PHY_CFG_WR_DISABLE 1
> +#define PHY_CFG_WR_DISABLE 0
> #define PHY_CFG_WR_SHIFT 0
> #define PHY_CFG_WR_MASK 1
> #define PHY_CFG_PLL_LOCK 0x10
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
next prev parent reply other threads:[~2025-06-30 8:49 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-29 12:47 [PATCH v7 0/4] PCI: rockchip: Improve driver quality Geraldo Nascimento
2025-06-29 12:47 ` [PATCH v7 1/4] PCI: rockchip: Use standard PCIe defines Geraldo Nascimento
2025-06-29 12:48 ` [PATCH v7 2/4] PCI: rockchip: Set Target Link Speed before retraining Geraldo Nascimento
2025-06-29 12:48 ` [PATCH v7 4/4] phy: rockchip-pcie: Properly disable TEST_WRITE strobe signal Geraldo Nascimento
2025-06-30 8:49 ` neil.armstrong [this message]
2025-06-29 20:58 ` [PATCH v7 3/4] phy: rockchip-pcie: Enable all four lanes if required Geraldo Nascimento
2025-06-30 8:49 ` neil.armstrong
2025-06-30 13:48 ` Robin Murphy
2025-06-30 17:55 ` Geraldo Nascimento
2025-07-21 14:52 ` Geraldo Nascimento
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