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[2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id l11-20020ac2554b000000b004f149967e87sm632931lfk.187.2023.05.06.05.04.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 06 May 2023 05:04:43 -0700 (PDT) Message-ID: Date: Sat, 6 May 2023 15:04:42 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH 5/8] PCI: qcom: Do not advertise hotplug capability for IP v2.3.2 Content-Language: en-GB To: Manivannan Sadhasivam , lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, steev@kali.org, quic_srichara@quicinc.com References: <20230506073139.8789-1-manivannan.sadhasivam@linaro.org> <20230506073139.8789-6-manivannan.sadhasivam@linaro.org> From: Dmitry Baryshkov In-Reply-To: <20230506073139.8789-6-manivannan.sadhasivam@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On 06/05/2023 10:31, Manivannan Sadhasivam wrote: > SoCs making use of Qcom PCIe controller IP v2.3.2 do not support hotplug > functionality. But the hotplug capability bit is set by default in the > hardware. This causes the kernel PCI core to register hotplug service for > the controller and send hotplug commands to it. But those commands will > timeout generating messages as below during boot and suspend/resume. > > [ 5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2020 msec ago) > [ 5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2048 msec ago) > [ 7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2020 msec ago) > [ 7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2052 msec ago) > > This not only spams the console output but also induces a delay of a > couple of seconds. To fix this issue, let's clear the HPC bit in > PCI_EXP_SLTCAP register as a part of the post init sequence to not > advertise the hotplug capability for the controller. > > Signed-off-by: Manivannan Sadhasivam > --- > drivers/pci/controller/dwc/pcie-qcom.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c > index 3d5b3ce9e2da..33353be396ec 100644 > --- a/drivers/pci/controller/dwc/pcie-qcom.c > +++ b/drivers/pci/controller/dwc/pcie-qcom.c > @@ -579,6 +579,8 @@ static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie) > > static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie) > { > + struct dw_pcie *pci = pcie->pci; > + u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > u32 val; > > /* enable PCIe clocks and resets */ > @@ -602,6 +604,14 @@ static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie) > val |= EN; > writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); > > + dw_pcie_dbi_ro_wr_en(pci); > + > + val = readl(pci->dbi_base + offset + PCI_EXP_SLTCAP); > + val &= ~PCI_EXP_SLTCAP_HPC; > + writel(val, pci->dbi_base + offset + PCI_EXP_SLTCAP); > + > + dw_pcie_dbi_ro_wr_dis(pci); > + Seeing this code again and again makes me wonder if we should have a separate function for this. -- With best wishes Dmitry