From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF203EB64DD for ; Tue, 27 Jun 2023 06:35:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230338AbjF0Gfz (ORCPT ); Tue, 27 Jun 2023 02:35:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38748 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230376AbjF0Gfs (ORCPT ); Tue, 27 Jun 2023 02:35:48 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 201282120; Mon, 26 Jun 2023 23:35:43 -0700 (PDT) Received: from pps.filterd (m0279864.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35R5fb1k022888; Tue, 27 Jun 2023 06:35:37 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=date : from : to : cc : subject : message-id : references : mime-version : content-type : in-reply-to; s=qcppdkim1; bh=a9/8jloY1SITJxs8vJeZOe0WCZbr/Y8PpK7/up/ZC74=; b=c0npUSlv2xavLM0a4TZJL7gGWVohOPl/xBrr2nfgTtG30zplWub8EiTuJtMIGz5uKC4O EVfu2gwGIqYUluz+a5OuM1KopcXu9NzTos1oKPOs6cfXyzGtxGKNxF3AwQjz8fG/H0Cp 2tLHxsTOYtJ/gNLljzrEfYYZxHwYLTioKFnuVBENAvVMHUnbY5D/m3FU1A8C64nJIZXV Uk/ehdYkEAMmhuTZKRw8IMhz/JC926Q9wytG75TMb9ZHgMSuo3EPgmfr1Fg32HzET8KX v6yp3hvEpBxfIBZGjSX5UJyGyc2THqHJdmL/gm5ZNUSleionduNDrVW1qRX0pZJJt5eb ZA== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rf8gtj85q-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 27 Jun 2023 06:35:37 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 35R6ZWRD019463 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 27 Jun 2023 06:35:32 GMT Received: from hu-pkondeti-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Mon, 26 Jun 2023 23:35:26 -0700 Date: Tue, 27 Jun 2023 12:05:23 +0530 From: Pavan Kondeti To: Krishna chaitanya chundru CC: , , , , , , , , , , "Manivannan Sadhasivam" , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas Subject: Re: [PATCH v5 3/3] PCI: qcom-ep: Add ICC bandwidth voting support Message-ID: References: <1687827692-6181-1-git-send-email-quic_krichai@quicinc.com> <1687827692-6181-4-git-send-email-quic_krichai@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <1687827692-6181-4-git-send-email-quic_krichai@quicinc.com> X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: R_B6GZJGrAR1eXskLMG0eWxB7lgNjBAJ X-Proofpoint-ORIG-GUID: R_B6GZJGrAR1eXskLMG0eWxB7lgNjBAJ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-27_03,2023-06-26_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 lowpriorityscore=0 priorityscore=1501 impostorscore=0 adultscore=0 malwarescore=0 spamscore=0 phishscore=0 mlxscore=0 clxscore=1011 mlxlogscore=753 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306270061 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On Tue, Jun 27, 2023 at 06:31:31AM +0530, Krishna chaitanya chundru wrote: > +static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep) > +{ > + struct dw_pcie *pci = &pcie_ep->pci; > + u32 offset, status, bw; > + int speed, width; > + int ret; > + > + if (!pcie_ep->icc_mem) > + return; > + Is this check needed? interconnect is added as required property and probe is failed if interconnect get fails. qcom_pcie_enable_resources() which gets called before enabling this interrupt is assuming that interconnect available. > + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > + status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); > + > + speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status); > + width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status); > + > + switch (speed) { > + case 1: > + bw = MBps_to_icc(PCIE_GEN1_BW_MBPS); > + break; > + case 2: > + bw = MBps_to_icc(PCIE_GEN2_BW_MBPS); > + break; > + case 3: > + bw = MBps_to_icc(PCIE_GEN3_BW_MBPS); > + break; > + default: > + dev_warn(pci->dev, "using default GEN4 bandwidth\n"); > + fallthrough; > + case 4: > + bw = MBps_to_icc(PCIE_GEN4_BW_MBPS); > + break; > + } > + > + ret = icc_set_bw(pcie_ep->icc_mem, 0, width * bw); > + if (ret) { > + dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", > + ret); > + } Are you not seeing the below warning from checkpatch? WARNING: braces {} are not necessary for single statement blocks > +} > + > static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) > { > int ret; > + struct dw_pcie *pci = &pcie_ep->pci; > > ret = clk_bulk_prepare_enable(pcie_ep->num_clks, pcie_ep->clks); > if (ret) > @@ -277,6 +331,20 @@ static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep) > if (ret) > goto err_phy_exit; > > + /* > + * Some Qualcomm platforms require interconnect bandwidth constraints > + * to be set before enabling interconnect clocks. > + * > + * Set an initial peak bandwidth corresponding to single-lane Gen 1 > + * for the pcie-mem path. > + */ > + ret = icc_set_bw(pcie_ep->icc_mem, 0, MBps_to_icc(PCIE_GEN1_BW_MBPS)); > + if (ret) { > + dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n", > + ret); > + goto err_phy_exit; > + } > + > return 0; Thanks, Pavan