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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ade1db55f6bsm906998066b.51.2025.06.11.08.31.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 11 Jun 2025 08:31:25 -0700 (PDT) Message-ID: Date: Wed, 11 Jun 2025 17:31:20 +0200 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/2] PCI: qcom: Add equalization settings for 8.0 GT/s To: Ziyue Zhang , andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, jingoohan1@gmail.com, mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org, bhelgaas@google.com, johan+linaro@kernel.org, vkoul@kernel.org, kishon@kernel.org, dmitry.baryshkov@linaro.org, manivannan.sadhasivam@linaro.org, neil.armstrong@linaro.org, abel.vesa@linaro.org, kw@linux.com Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-phy@lists.infradead.org, qiang.yu@oss.qualcomm.com, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com References: <20250611100319.464803-1-quic_ziyuzhan@quicinc.com> <20250611100319.464803-2-quic_ziyuzhan@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250611100319.464803-2-quic_ziyuzhan@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNjExMDEzMCBTYWx0ZWRfX4m4A2PQ6UPDW ea3VJ9UcpRZvYaeHbSj5/azu99+ztKEmW4cyQLbWFYCUYKPXaEt4m5GUfeyBvfDDGae382l+wYc Eq7iC/a11ws1QH3/Bv7xwChh81oaAw/fluFIFb8C3RgWd+N5ynmIQOjYGP/VQhEMtnPjnfHsUBA 1eRNnsVIXCEQIX366gIWW4uXVppNzAwoRZXaLtnvOLW8N8GKRGw6B0Q9Bl9EBFnGAtIaaj4OAAW MYFJXwW1US0IMGKLLALvrnewgB6p1cjJ/fLKzSvCD5FVOSGMX0eWafQeMc2fRwG6Eh+uMcYvyB1 5sdZ8r9BjesTh2YN1cX43T3t7v+fFDiy0bi4gDldMDxsnrERkm/PI7WGijnYWITZzMsi5RgBsTu PmV126tmnwUk1Uns+kiaJu8LqzWcc9mJkPJ4f6utunAm8UbHNTYi6OUY9ThsphQGJf+52Lvp X-Authority-Analysis: v=2.4 cv=Q7TS452a c=1 sm=1 tr=0 ts=6849a152 cx=c_pps a=wEM5vcRIz55oU/E2lInRtA==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=6IFa9wvqVegA:10 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=XRhAMW6oQtNP-qC2JosA:9 a=QEXdDO2ut3YA:10 a=OIgjcC2v60KrkQgK7BGD:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: 4OLlxFB3XP164tug0d1gS3XHUcxvdr5T X-Proofpoint-ORIG-GUID: 4OLlxFB3XP164tug0d1gS3XHUcxvdr5T X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-11_05,2025-06-10_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 mlxscore=0 spamscore=0 mlxlogscore=999 bulkscore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 impostorscore=0 priorityscore=1501 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2506110130 On 6/11/25 12:03 PM, Ziyue Zhang wrote: > Adding lane equalization setting for 8.0 GT/s to enhance link stability > and fix AER correctable errors reported on some platforms (eg. SA8775P). > > 8.0 GT/s and 16.0GT/s require the same equalization setting. This setting > is programmed into a group of shadow registers, which can be switched to > configure equalization for different GEN speeds by writing 00b, 01b > to `RATE_SHADOW_SEL`. > > Hence program equalization registers in a loop using link speed as index, > so that equalization setting can be programmed for both 8.0 GT/s and > 16.0 GT/s. > > Co-developed-by: Qiang Yu > Signed-off-by: Qiang Yu > Signed-off-by: Ziyue Zhang > --- [...] > -void qcom_pcie_common_set_16gt_equalization(struct dw_pcie *pci) > +void qcom_pcie_common_set_equalization(struct dw_pcie *pci) > { > u32 reg; > + u16 speed, max_speed = PCIE_SPEED_16_0GT; > + struct device *dev = pci->dev; > > /* > * GEN3_RELATED_OFF register is repurposed to apply equalization > @@ -18,33 +20,43 @@ void qcom_pcie_common_set_16gt_equalization(struct dw_pcie *pci) > * GEN3_EQ_*. The RATE_SHADOW_SEL bit field of GEN3_RELATED_OFF > * determines the data rate for which these equalization settings are > * applied. > + * > + * TODO: > + * EQ settings need to be added for 32.0 T/s in future > */ > - reg = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); > - reg &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; > - reg &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; > - reg |= FIELD_PREP(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, > - GEN3_RELATED_OFF_RATE_SHADOW_SEL_16_0GT); > - dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, reg); > + if (pcie_link_speed[pci->max_link_speed] < PCIE_SPEED_32_0GT) > + max_speed = pcie_link_speed[pci->max_link_speed]; > + else > + dev_warn(dev, "The target supports 32.0 GT/s, but the EQ setting for 32.0 GT/s is not configured.\n"); > > - reg = dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF); > - reg &= ~(GEN3_EQ_FMDC_T_MIN_PHASE23 | > - GEN3_EQ_FMDC_N_EVALS | > - GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA | > - GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA); > - reg |= FIELD_PREP(GEN3_EQ_FMDC_T_MIN_PHASE23, 0x1) | > - FIELD_PREP(GEN3_EQ_FMDC_N_EVALS, 0xd) | > - FIELD_PREP(GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA, 0x5) | > - FIELD_PREP(GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA, 0x5); > - dw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg); > + for (speed = PCIE_SPEED_8_0GT; speed <= max_speed; ++speed) { > + reg = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF); > + reg &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL; > + reg &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK; > + reg |= FIELD_PREP(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK, > + speed - PCIE_SPEED_8_0GT); > + dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, reg); > > - reg = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); > - reg &= ~(GEN3_EQ_CONTROL_OFF_FB_MODE | > - GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE | > - GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL | > - GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC); > - dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg); > + reg = dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF); > + reg &= ~(GEN3_EQ_FMDC_T_MIN_PHASE23 | > + GEN3_EQ_FMDC_N_EVALS | > + GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA | > + GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA); > + reg |= FIELD_PREP(GEN3_EQ_FMDC_T_MIN_PHASE23, 0x1) | > + FIELD_PREP(GEN3_EQ_FMDC_N_EVALS, 0xd) | > + FIELD_PREP(GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA, 0x5) | > + FIELD_PREP(GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA, 0x5); > + dw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg); > + > + reg = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF); > + reg &= ~(GEN3_EQ_CONTROL_OFF_FB_MODE | > + GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE | > + GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL | > + GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC); > + dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg); > + } this function could receive `speed` as a parameter instead, so that it's easier to parse Konrad