Re: [PATCH 4/5] PCI: rzg3s-host: Prepare System Controller handling for multiple PCIe channels

[Claudiu Beznea <claudiu.beznea@tuxon.dev>]

Hi, Prabhakar,

On 3/18/26 14:44, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Prepare the driver to handle multiple PCIe channels with distinct System
> Controller register sets, as required by RZ/V2H(P). The current design
> stores a single sysc_info structure per SoC, which is insufficient for
> multi-channel configurations.
> 
> Introduce channel identifiers and extend struct rzg3s_pcie_soc_data to
> hold a sysc_info array indexed per PCIe channel. Add a channel field to
> struct rzg3s_pcie_host and select the appropriate System Controller
> information during probe based on the channel.
> 
> Keep existing single-channel SoCs functionally unchanged while
> preparing the driver for RZ/V2H(P) multi-channel support.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>   drivers/pci/controller/pcie-rzg3s-host.c | 48 ++++++++++++++++--------
>   1 file changed, 33 insertions(+), 15 deletions(-)
> 
> diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/controller/pcie-rzg3s-host.c
> index c61e011f8302..a629e861bbd0 100644
> --- a/drivers/pci/controller/pcie-rzg3s-host.c
> +++ b/drivers/pci/controller/pcie-rzg3s-host.c
> @@ -241,6 +241,18 @@ struct rzg3s_pcie_msi {
>   	int irq;
>   };
>   
> +/**
> + * enum rzg3s_pcie_channel_id - RZ/G3S PCIe channel IDs
> + * @RZG3S_PCIE_CHANNEL_ID_0: PCIe channel 0
> + * @RZG3S_PCIE_CHANNEL_ID_1: PCIe channel 1
> + * @RZG3S_PCIE_CHANNEL_ID_MAX: Max PCIe channels
> + */
> +enum rzg3s_pcie_channel_id {
> +	RZG3S_PCIE_CHANNEL_ID_0,
> +	RZG3S_PCIE_CHANNEL_ID_1,

Just saying... based on Bjorn feedback on patch 3/5 the names used here would 
have to be adjusted accordingly. Maybe controller_id? Same for the other patches.

Thank you,
Claudiu