[PATCH 0/3] Relax max-link-speed check to support PCIe Gen5/Gen6

[PATCH 0/3] Relax max-link-speed check to support PCIe Gen5/Gen6

[Hans Zhang]

This patch series extends PCIe Gen5/Gen6 support for the max-link-speed
property across device tree bindings and kernel validation logic.

With PCIe 6.0 now supported in the Linux kernel and industry IP providers
like Synopsys/Cadence offering PCIe 6.0-compatible IPs, existing device
tree bindings and checks for max-link-speed (limited to Gen1~Gen4) no
longer align with hardware capabilities.

Documentation updates:

Patch 1/3 extends the PCI host controller binding (pci.txt) to explicitly
include Gen5/Gen6.

Patch 2/3 updates the PCI endpoint binding (pci-ep.yaml) with the same
extension.

Kernel validation fix:

Patch 3/3 relaxes the max-link-speed check in of_pci_get_max_link_speed()
to accept values up to 6, ensuring compatibility with newer generations.

These changes ensure that device tree configurations for modern PCIe
controllers (e.g., Synopsys/Cadence IP-based designs) can fully utilize
Gen5/Gen6 speeds without DT validation errors.

---
In my impression, they have already obtained the relevant certifications.

e.g.:
Synopsys:
https://www.synopsys.com/dw/ipdir.php?ds=dwc_pcie6_controller

Cadence:
https://www.cadence.com/en_US/home/tools/silicon-solutions/protocol-ip/pcie-and-compute-express-link/controller-for-pcie-and-cxl/controller-for-pcie.html
---

Hans Zhang (3):
  dt-bindings: PCI: Extend max-link-speed to support PCIe Gen5/Gen6
  dt-bindings: PCI: pci-ep: Extend max-link-speed to PCIe Gen5/Gen6
  PCI: of: Relax max-link-speed check to support PCIe Gen5/Gen6

 Documentation/devicetree/bindings/pci/pci-ep.yaml | 2 +-
 Documentation/devicetree/bindings/pci/pci.txt     | 5 +++--
 drivers/pci/of.c                                  | 2 +-
 3 files changed, 5 insertions(+), 4 deletions(-)


base-commit: fee3e843b309444f48157e2188efa6818bae85cf
-- 
2.25.1

[PATCH 1/3] dt-bindings: PCI: Extend max-link-speed to support PCIe Gen5/Gen6

[Hans Zhang]

Update the device tree binding documentation for PCI to include
PCIe Gen5 and Gen6 support in the `max-link-speed` property.
The original documentation limited the value to 1~4 (Gen1~Gen4),
but the kernel now supports up to Gen6. This change ensures the
documentation aligns with the actual code implementation.

Signed-off-by: Hans Zhang <18255117159@163.com>
---
 Documentation/devicetree/bindings/pci/pci.txt | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt
index 6a8f2874a24d..5ffd690e3fc7 100644
--- a/Documentation/devicetree/bindings/pci/pci.txt
+++ b/Documentation/devicetree/bindings/pci/pci.txt
@@ -22,8 +22,9 @@ driver implementation may support the following properties:
    If present this property specifies PCI gen for link capability.  Host
    drivers could add this as a strategy to avoid unnecessary operation for
    unsupported link speed, for instance, trying to do training for
-   unsupported link speed, etc.  Must be '4' for gen4, '3' for gen3, '2'
-   for gen2, and '1' for gen1. Any other values are invalid.
+   unsupported link speed, etc.  Must be '6' for gen6, '5' for gen5, '4' for
+   gen4, '3' for gen3, '2' for gen2, and '1' for gen1. Any other values are
+   invalid.
 - reset-gpios:
    If present this property specifies PERST# GPIO. Host drivers can parse the
    GPIO and apply fundamental reset to endpoints.
-- 
2.25.1

[PATCH 2/3] dt-bindings: PCI: pci-ep: Extend max-link-speed to PCIe Gen5/Gen6

[Hans Zhang]

Update the PCI Endpoint (EP) device tree binding documentation to
include PCIe Gen5 and Gen6 support for the `max-link-speed` property.
Similar to the Host Controller binding, the original EP binding
limited this value to 1~4 (Gen1~Gen4). With current SOCs requiring
Gen5/Gen6 support (e.g., Synopsys/Cadence IP), this change aligns
the EP binding with the kernel's PCIe 6.0 capabilities.

Signed-off-by: Hans Zhang <18255117159@163.com>
---
 Documentation/devicetree/bindings/pci/pci-ep.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/pci/pci-ep.yaml b/Documentation/devicetree/bindings/pci/pci-ep.yaml
index f75000e3093d..68aaad70b112 100644
--- a/Documentation/devicetree/bindings/pci/pci-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/pci-ep.yaml
@@ -33,7 +33,7 @@ properties:
 
   max-link-speed:
     $ref: /schemas/types.yaml#/definitions/uint32
-    enum: [ 1, 2, 3, 4 ]
+    enum: [ 1, 2, 3, 4, 5, 6]
 
   num-lanes:
     description: maximum number of lanes
-- 
2.25.1

[PATCH 3/3] PCI: of: Relax max-link-speed check to support PCIe Gen5/Gen6

[Hans Zhang]

The existing code restricted `max-link-speed` to values 1~4 (Gen1~Gen4),
but current SOCs using Synopsys/Cadence IP may require Gen5/Gen6 support.
This patch updates the validation in `of_pci_get_max_link_speed` to allow
values up to 6, ensuring compatibility with newer PCIe generations.

Signed-off-by: Hans Zhang <18255117159@163.com>
---
 drivers/pci/of.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/pci/of.c b/drivers/pci/of.c
index ab7a8252bf41..379d90913937 100644
--- a/drivers/pci/of.c
+++ b/drivers/pci/of.c
@@ -890,7 +890,7 @@ int of_pci_get_max_link_speed(struct device_node *node)
 	u32 max_link_speed;
 
 	if (of_property_read_u32(node, "max-link-speed", &max_link_speed) ||
-	    max_link_speed == 0 || max_link_speed > 4)
+	    max_link_speed == 0 || max_link_speed > 6)
 		return -EINVAL;
 
 	return max_link_speed;
-- 
2.25.1

Re: [PATCH 1/3] dt-bindings: PCI: Extend max-link-speed to support PCIe Gen5/Gen6

[Rob Herring]

On Tue, May 20, 2025 at 12:04:46AM +0800, Hans Zhang wrote:
> Update the device tree binding documentation for PCI to include
> PCIe Gen5 and Gen6 support in the `max-link-speed` property.
> The original documentation limited the value to 1~4 (Gen1~Gen4),
> but the kernel now supports up to Gen6. This change ensures the
> documentation aligns with the actual code implementation.
> 
> Signed-off-by: Hans Zhang <18255117159@163.com>
> ---
>  Documentation/devicetree/bindings/pci/pci.txt | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)

This file is now removed. Update the schema if you need to. It lives in 
dtschema project.

> 
> diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt
> index 6a8f2874a24d..5ffd690e3fc7 100644
> --- a/Documentation/devicetree/bindings/pci/pci.txt
> +++ b/Documentation/devicetree/bindings/pci/pci.txt
> @@ -22,8 +22,9 @@ driver implementation may support the following properties:
>     If present this property specifies PCI gen for link capability.  Host
>     drivers could add this as a strategy to avoid unnecessary operation for
>     unsupported link speed, for instance, trying to do training for
> -   unsupported link speed, etc.  Must be '4' for gen4, '3' for gen3, '2'
> -   for gen2, and '1' for gen1. Any other values are invalid.
> +   unsupported link speed, etc.  Must be '6' for gen6, '5' for gen5, '4' for
> +   gen4, '3' for gen3, '2' for gen2, and '1' for gen1. Any other values are
> +   invalid.
>  - reset-gpios:
>     If present this property specifies PERST# GPIO. Host drivers can parse the
>     GPIO and apply fundamental reset to endpoints.
> -- 
> 2.25.1
> 

Re: [PATCH 2/3] dt-bindings: PCI: pci-ep: Extend max-link-speed to PCIe Gen5/Gen6

[Rob Herring (Arm)]

On Tue, 20 May 2025 00:04:47 +0800, Hans Zhang wrote:
> Update the PCI Endpoint (EP) device tree binding documentation to
> include PCIe Gen5 and Gen6 support for the `max-link-speed` property.
> Similar to the Host Controller binding, the original EP binding
> limited this value to 1~4 (Gen1~Gen4). With current SOCs requiring
> Gen5/Gen6 support (e.g., Synopsys/Cadence IP), this change aligns
> the EP binding with the kernel's PCIe 6.0 capabilities.
> 
> Signed-off-by: Hans Zhang <18255117159@163.com>
> ---
>  Documentation/devicetree/bindings/pci/pci-ep.yaml | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH 1/3] dt-bindings: PCI: Extend max-link-speed to support PCIe Gen5/Gen6

[Hans Zhang]

On 2025/5/28 03:35, Rob Herring wrote:
> On Tue, May 20, 2025 at 12:04:46AM +0800, Hans Zhang wrote:
>> Update the device tree binding documentation for PCI to include
>> PCIe Gen5 and Gen6 support in the `max-link-speed` property.
>> The original documentation limited the value to 1~4 (Gen1~Gen4),
>> but the kernel now supports up to Gen6. This change ensures the
>> documentation aligns with the actual code implementation.
>>
>> Signed-off-by: Hans Zhang <18255117159@163.com>
>> ---
>>   Documentation/devicetree/bindings/pci/pci.txt | 5 +++--
>>   1 file changed, 3 insertions(+), 2 deletions(-)
> 
> This file is now removed. Update the schema if you need to. It lives in
> dtschema project.
> 

Dear Rob,

Thank you very much for your reply and reminder. I will resubmit in the 
next version.

Best regards,
Hans

>>
>> diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt
>> index 6a8f2874a24d..5ffd690e3fc7 100644
>> --- a/Documentation/devicetree/bindings/pci/pci.txt
>> +++ b/Documentation/devicetree/bindings/pci/pci.txt
>> @@ -22,8 +22,9 @@ driver implementation may support the following properties:
>>      If present this property specifies PCI gen for link capability.  Host
>>      drivers could add this as a strategy to avoid unnecessary operation for
>>      unsupported link speed, for instance, trying to do training for
>> -   unsupported link speed, etc.  Must be '4' for gen4, '3' for gen3, '2'
>> -   for gen2, and '1' for gen1. Any other values are invalid.
>> +   unsupported link speed, etc.  Must be '6' for gen6, '5' for gen5, '4' for
>> +   gen4, '3' for gen3, '2' for gen2, and '1' for gen1. Any other values are
>> +   invalid.
>>   - reset-gpios:
>>      If present this property specifies PERST# GPIO. Host drivers can parse the
>>      GPIO and apply fundamental reset to endpoints.
>> -- 
>> 2.25.1
>>