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From: Stanimir Varbanov <svarbanov@suse.de>
To: Jim Quinlan <james.quinlan@broadcom.com>,
	linux-pci@vger.kernel.org,
	Nicolas Saenz Julienne <nsaenz@kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Cyril Brulebois <kibi@debian.org>,
	Stanimir Varbanov <svarbanov@suse.de>,
	bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com
Cc: "Florian Fainelli" <florian.fainelli@broadcom.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Rob Herring" <robh@kernel.org>,
	"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
	<linux-rpi-kernel@lists.infradead.org>,
	"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE"
	<linux-arm-kernel@lists.infradead.org>,
	"open list" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v1 6/8] PCI: brcmstb: Don't conflate the reset rescal with phy ctrl
Date: Tue, 2 Jul 2024 16:10:19 +0300	[thread overview]
Message-ID: <c4633d7a-11a4-4c1c-954b-45f631cb2563@suse.de> (raw)
In-Reply-To: <20240628205430.24775-7-james.quinlan@broadcom.com>



On 6/28/24 23:54, Jim Quinlan wrote:
> We've been assuming that if an SOC has a "rescal" reset controller that we
> should automatically invoke brcm_phy_cntl(...).  This will not be true in
> future SOCs, so we create a bool "has_phy" and adjust the cfg_data
> appropriately (we need to give 7216 its own cfg_data structure instead of
> sharing one).
> 
> Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
> ---
>  drivers/pci/controller/pcie-brcmstb.c | 17 ++++++++++++++---
>  1 file changed, 14 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
> index 4e0848e1311f..e740e2966a5c 100644
> --- a/drivers/pci/controller/pcie-brcmstb.c
> +++ b/drivers/pci/controller/pcie-brcmstb.c
> @@ -227,6 +227,7 @@ enum pcie_type {
>  struct pcie_cfg_data {
>  	const int *offsets;
>  	const enum pcie_type type;
> +	const bool has_phy;
>  	void (*perst_set)(struct brcm_pcie *pcie, u32 val);
>  	void (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
>  };
> @@ -277,6 +278,7 @@ struct brcm_pcie {
>  	void			(*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
>  	struct subdev_regulators *sr;
>  	bool			ep_wakeup_capable;
> +	bool			has_phy;
>  };
>  
>  static inline bool is_bmips(const struct brcm_pcie *pcie)
> @@ -1316,12 +1318,12 @@ static int brcm_phy_cntl(struct brcm_pcie *pcie, const int start)
>  
>  static inline int brcm_phy_start(struct brcm_pcie *pcie)
>  {
> -	return pcie->rescal ? brcm_phy_cntl(pcie, 1) : 0;
> +	return pcie->has_phy ? brcm_phy_cntl(pcie, 1) : 0;
>  }
>  
>  static inline int brcm_phy_stop(struct brcm_pcie *pcie)
>  {
> -	return pcie->rescal ? brcm_phy_cntl(pcie, 0) : 0;
> +	return pcie->has_phy ? brcm_phy_cntl(pcie, 0) : 0;
>  }
>  
>  static void brcm_pcie_turn_off(struct brcm_pcie *pcie)
> @@ -1564,12 +1566,20 @@ static const struct pcie_cfg_data bcm2711_cfg = {
>  	.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_generic,
>  };
>  
> +static const struct pcie_cfg_data bcm7216_cfg = {
> +	.offsets	= pcie_offset_bcm7278,
> +	.type		= BCM7278,

This "type" field is confusing, maybe it would be good to rename it to
"family"? For example BCM72XX family.

> +	.perst_set	= brcm_pcie_perst_set_7278,
> +	.bridge_sw_init_set = brcm_pcie_bridge_sw_init_set_7278,
> +	.has_phy	= true,
> +};
> +
>  static const struct of_device_id brcm_pcie_match[] = {
>  	{ .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
>  	{ .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
>  	{ .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg },
>  	{ .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
> -	{ .compatible = "brcm,bcm7216-pcie", .data = &bcm7278_cfg },
> +	{ .compatible = "brcm,bcm7216-pcie", .data = &bcm7216_cfg },
>  	{ .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
>  	{ .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
>  	{ .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
> @@ -1617,6 +1627,7 @@ static int brcm_pcie_probe(struct platform_device *pdev)
>  	pcie->type = data->type;
>  	pcie->perst_set = data->perst_set;
>  	pcie->bridge_sw_init_set = data->bridge_sw_init_set;
> +	pcie->has_phy = data->has_phy;
>  
>  	pcie->base = devm_platform_ioremap_resource(pdev, 0);
>  	if (IS_ERR(pcie->base))

~Stan

  reply	other threads:[~2024-07-02 13:10 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-28 20:54 [PATCH v1 0/8] PCI: brcnstb: Enable STB 7712 SOC Jim Quinlan
2024-06-28 20:54 ` [PATCH v1 1/8] dt-bindings: PCI: Add Broadcom STB 7712 SOC, update maintainter Jim Quinlan
2024-07-01  9:12   ` Krzysztof Kozlowski
2024-07-02 21:57     ` Jim Quinlan
2024-07-03  4:33       ` Krzysztof Kozlowski
2024-07-01 19:47   ` Bjorn Helgaas
2024-06-28 20:54 ` [PATCH v1 2/8] PCI: brcmstb: Use "clk_out" error path label Jim Quinlan
2024-07-01 19:49   ` Bjorn Helgaas
2024-07-03 18:45   ` [PATCH " Markus Elfring
2024-06-28 20:54 ` [PATCH v1 3/8] PCI: brcmstb: Use bridge reset if available Jim Quinlan
2024-07-02 12:59   ` Stanimir Varbanov
2024-07-02 18:36     ` Jim Quinlan
2024-07-03 13:09       ` Stanimir Varbanov
2024-06-28 20:54 ` [PATCH v1 4/8] PCI: brcmstb: Use swinit " Jim Quinlan
2024-07-01  9:48   ` Philipp Zabel
2024-07-02 13:02   ` Stanimir Varbanov
2024-06-28 20:54 ` [PATCH v1 5/8] PCI: brcmstb: Two more register offsets vary by SOC Jim Quinlan
2024-07-01  3:23   ` kernel test robot
2024-07-01 17:32   ` Bjorn Helgaas
2024-06-28 20:54 ` [PATCH v1 6/8] PCI: brcmstb: Don't conflate the reset rescal with phy ctrl Jim Quinlan
2024-07-02 13:10   ` Stanimir Varbanov [this message]
2024-07-02 17:59     ` Jim Quinlan
2024-07-03 12:38       ` Stanimir Varbanov
2024-06-28 20:54 ` [PATCH v1 7/8] PCI: brcmstb: Refactor for chips with many regular inbound BARs Jim Quinlan
2024-06-28 20:54 ` [PATCH v1 8/8] PCI: brcmstb: Enable 7712 SOCs Jim Quinlan

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