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From: Florian Fainelli <f.fainelli@gmail.com>
To: Jim Quinlan <james.quinlan@broadcom.com>,
	Philipp Zabel <pza@pengutronix.de>
Cc: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Rob Herring <robh@kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	"maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE" 
	<bcm-kernel-feedback-list@broadcom.com>,
	"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" 
	<linux-rpi-kernel@lists.infradead.org>,
	"moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE" 
	<linux-arm-kernel@lists.infradead.org>,
	"open list:PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS" 
	<linux-pci@vger.kernel.org>,
	open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 07/15] PCI: brcmstb: Add control of rescal reset
Date: Mon, 25 May 2020 09:58:33 -0700	[thread overview]
Message-ID: <c76cc2e6-fcc5-5d42-5ff1-770a99cb9b13@gmail.com> (raw)
In-Reply-To: <CA+-6iNxtW66QLrb5BaOOCPJwG-1fShdfZqiLSkKfi6Y669dn5w@mail.gmail.com>



On 5/21/2020 2:48 PM, Jim Quinlan wrote:
> On Wed, May 20, 2020 at 3:27 AM Philipp Zabel <pza@pengutronix.de> wrote:
>>
>> Hi Jim,
>>
>> On Tue, May 19, 2020 at 04:34:05PM -0400, Jim Quinlan wrote:
>>> From: Jim Quinlan <jquinlan@broadcom.com>
>>>
>>> Some STB chips have a special purpose reset controller named
>>> RESCAL (reset calibration).  This commit adds the control
>>> of RESCAL as well as the ability to start and stop its
>>> operation for PCIe HW.
>>>
>>> Signed-off-by: Jim Quinlan <jquinlan@broadcom.com>
>>> ---
>>>  drivers/pci/controller/pcie-brcmstb.c | 81 ++++++++++++++++++++++++++-
>>>  1 file changed, 80 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
>>> index 2c470104ba38..0787e8f6f7e5 100644
>>> --- a/drivers/pci/controller/pcie-brcmstb.c
>>> +++ b/drivers/pci/controller/pcie-brcmstb.c
>> [...]
>>> @@ -1100,6 +1164,21 @@ static int brcm_pcie_probe(struct platform_device *pdev)
>>>               dev_err(&pdev->dev, "could not enable clock\n");
>>>               return ret;
>>>       }
>>> +     pcie->rescal = devm_reset_control_get_shared(&pdev->dev, "rescal");
>>> +     if (IS_ERR(pcie->rescal)) {
>>> +             if (PTR_ERR(pcie->rescal) == -EPROBE_DEFER)
>>> +                     return -EPROBE_DEFER;
>>> +             pcie->rescal = NULL;
>>
>> This is effectively an optional reset control, so it is better to use:
>> ↵
>>         pcie->rescal = devm_reset_control_get_optional_shared(&pdev->dev,
>>                                                               "rescal");↵
>>         if (IS_ERR(pcie->rescal))
>>                 return PTR_ERR(pcie->rescal);
>>
>>> +     } else {
>>> +             ret = reset_control_deassert(pcie->rescal);
>>> +             if (ret)
>>> +                     dev_err(&pdev->dev, "failed to deassert 'rescal'\n");
>>> +     }
>>
>> reset_control_* can handle rstc == NULL parameters for optional reset
>> controls, so this can be done unconditionally:
>>
>>         ret = reset_control_deassert(pcie->rescal);↵
>>         if (ret)↵
>>                 dev_err(&pdev->dev, "failed to deassert 'rescal'\n");↵
>>
>> Is rescal handled by the reset-brcmstb-rescal driver? Since that only
>> implements the .reset op, I would expect reset_control_reset() here.
> Where exactly?  "reset.h" says that "Calling reset_control_rese()t is
> not allowed on a shared reset control." so I'm not sure why  you would
> want me to invoke it.

Yes this is handled by drivers/reset/reset-brcmstb-rescal.c which only
implements a .reset() callback, what would be the appropriate API usage
here given that this is a shared reset between AHCI and PCIe, should
drivers/reset/reset-brcmstb-rescal.c not implement a .reset() callback
and .assert() callback instead?

>> Otherwise this looks like it'd be missing a reset_control_assert in
>> remove.
> I can add this.
> Thanks,
> Jim
>>
>> regards
>> Philipp

-- 
Florian

  reply	other threads:[~2020-05-25 16:58 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-19 20:33 [PATCH 00/15] PCI: brcmstb: enable PCIe for STB chips Jim Quinlan
2020-05-19 20:33 ` [PATCH 01/15] PCI: brcmstb: PCIE_BRCMSTB depends on ARCH_BRCMSTB Jim Quinlan
2020-05-19 20:48   ` Florian Fainelli
2020-05-19 20:34 ` [PATCH 03/15] dt-bindings: PCI: Add bindings for more Brcmstb chips Jim Quinlan
2020-05-19 20:34 ` [PATCH 04/15] PCI: brcmstb: Add compatibily of other chips Jim Quinlan
2020-05-20 11:51   ` Nicolas Saenz Julienne
2020-05-20 14:30     ` Jim Quinlan
2020-05-20 14:41       ` Nicolas Saenz Julienne
2020-05-21 19:35     ` Jim Quinlan
2020-05-22  9:17       ` Nicolas Saenz Julienne
2020-05-19 20:34 ` [PATCH 05/15] PCI: brcmstb: Add suspend and resume pm_ops Jim Quinlan
2020-05-19 20:34 ` [PATCH 06/15] PCI: brcmstb: Asserting PERST is different for 7278 Jim Quinlan
2020-05-19 20:34 ` [PATCH 07/15] PCI: brcmstb: Add control of rescal reset Jim Quinlan
2020-05-20  7:27   ` Philipp Zabel
2020-05-21 21:48     ` Jim Quinlan
2020-05-25 16:58       ` Florian Fainelli [this message]
2020-05-19 20:34 ` [PATCH 12/15] PCI: brcmstb: Set internal memory viewport sizes Jim Quinlan
2020-05-19 20:34 ` [PATCH 13/15] PCI: brcmstb: Accommodate MSI for older chips Jim Quinlan
2020-05-19 20:34 ` [PATCH 14/15] PCI: brcmstb: Set bus max burst side by chip type Jim Quinlan
2020-05-20 13:44   ` Nicolas Saenz Julienne
2020-05-20 14:27     ` Jim Quinlan
2020-05-19 20:34 ` [PATCH 15/15] PCI: brcmstb: add compatilbe chips to match list Jim Quinlan
2020-05-20 16:15 ` [PATCH 00/15] PCI: brcmstb: enable PCIe for STB chips Bjorn Helgaas

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