[PATCH] PCI/P2PDMA: Update device table with 3rd gen Xeon platform information

[PATCH] PCI/P2PDMA: Update device table with 3rd gen Xeon platform information

[Michael J. Ruhl]

In order to do P2P communication the bridge ID of the platform
must be in the P2P device table.

Update the P2P device table with a device id for the 3rd Gen
Intel Xeon Scalable Processors.

Reviewed-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Michael J. Ruhl <michael.j.ruhl@intel.com>
---
 drivers/pci/p2pdma.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/pci/p2pdma.c b/drivers/pci/p2pdma.c
index 1015274bd2fe..30b1df3c9d2f 100644
--- a/drivers/pci/p2pdma.c
+++ b/drivers/pci/p2pdma.c
@@ -321,6 +321,7 @@ static const struct pci_p2pdma_whitelist_entry {
 	{PCI_VENDOR_ID_INTEL,	0x2032, 0},
 	{PCI_VENDOR_ID_INTEL,	0x2033, 0},
 	{PCI_VENDOR_ID_INTEL,	0x2020, 0},
+	{PCI_VENDOR_ID_INTEL,	0x09a2, 0},
 	{}
 };
 
-- 
2.31.1

RE: [PATCH] PCI/P2PDMA: Update device table with 3rd gen Xeon platform information

[Ruhl, Michael J]

Hi,

I see that this patch is in the Linux PCI development patchwork.

I am not sure what the timeline for this process is.

Will this be accepted or rejected "officially"?

Do I need to do anything else to move this patch forward?

Thanks,

Mike

>-----Original Message-----
>From: Ruhl, Michael J <michael.j.ruhl@intel.com>
>Sent: Wednesday, February 9, 2022 11:28 AM
>To: linux-pci@vger.kernel.org; linux-kernel@vger.kernel.org;
>bhelgaas@google.com; logang@deltatee.com; Ruhl, Michael J
><michael.j.ruhl@intel.com>
>Cc: Williams, Dan J <dan.j.williams@intel.com>
>Subject: [PATCH] PCI/P2PDMA: Update device table with 3rd gen Xeon
>platform information
>
>In order to do P2P communication the bridge ID of the platform
>must be in the P2P device table.
>
>Update the P2P device table with a device id for the 3rd Gen
>Intel Xeon Scalable Processors.
>
>Reviewed-by: Dan Williams <dan.j.williams@intel.com>
>Signed-off-by: Michael J. Ruhl <michael.j.ruhl@intel.com>
>---
> drivers/pci/p2pdma.c | 1 +
> 1 file changed, 1 insertion(+)
>
>diff --git a/drivers/pci/p2pdma.c b/drivers/pci/p2pdma.c
>index 1015274bd2fe..30b1df3c9d2f 100644
>--- a/drivers/pci/p2pdma.c
>+++ b/drivers/pci/p2pdma.c
>@@ -321,6 +321,7 @@ static const struct pci_p2pdma_whitelist_entry {
> 	{PCI_VENDOR_ID_INTEL,	0x2032, 0},
> 	{PCI_VENDOR_ID_INTEL,	0x2033, 0},
> 	{PCI_VENDOR_ID_INTEL,	0x2020, 0},
>+	{PCI_VENDOR_ID_INTEL,	0x09a2, 0},
> 	{}
> };
>
>--
>2.31.1

Re: [PATCH] PCI/P2PDMA: Update device table with 3rd gen Xeon platform information

[Bjorn Helgaas]

On Wed, Feb 09, 2022 at 11:28:01AM -0500, Michael J. Ruhl wrote:
> In order to do P2P communication the bridge ID of the platform
> must be in the P2P device table.
> 
> Update the P2P device table with a device id for the 3rd Gen
> Intel Xeon Scalable Processors.
> 
> Reviewed-by: Dan Williams <dan.j.williams@intel.com>
> Signed-off-by: Michael J. Ruhl <michael.j.ruhl@intel.com>

Updated the commit log to match previous similar patches and applied
as below to pci/p2pdma for v5.18, thanks!

Device ID 0x09a2 doesn't appear at https://pci-ids.ucw.cz/read/PC/8086
which means "lspci" won't be able to display a human-readable name for
these devices.  You can easily add a name at that same URL.

Bjorn


  commit feaea1fe8b36 ("PCI/P2PDMA: Add Intel 3rd Gen Intel Xeon Scalable Processors to whitelist")
  Author: Michael J. Ruhl <michael.j.ruhl@intel.com>
  Date:   Wed Feb 9 11:28:01 2022 -0500

    PCI/P2PDMA: Add Intel 3rd Gen Intel Xeon Scalable Processors to whitelist
    
    In order to do P2P communication the bridge ID of the platform must be in
    the P2P device table.
    
    Update the P2P device table with a device ID for the 3rd Gen Intel Xeon
    Scalable Processors.
    
    Link: https://lore.kernel.org/r/20220209162801.7647-1-michael.j.ruhl@intel.com
    Signed-off-by: Michael J. Ruhl <michael.j.ruhl@intel.com>
    Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
    Reviewed-by: Dan Williams <dan.j.williams@intel.com>

> ---
>  drivers/pci/p2pdma.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/pci/p2pdma.c b/drivers/pci/p2pdma.c
> index 1015274bd2fe..30b1df3c9d2f 100644
> --- a/drivers/pci/p2pdma.c
> +++ b/drivers/pci/p2pdma.c
> @@ -321,6 +321,7 @@ static const struct pci_p2pdma_whitelist_entry {
>  	{PCI_VENDOR_ID_INTEL,	0x2032, 0},
>  	{PCI_VENDOR_ID_INTEL,	0x2033, 0},
>  	{PCI_VENDOR_ID_INTEL,	0x2020, 0},
> +	{PCI_VENDOR_ID_INTEL,	0x09a2, 0},
>  	{}
>  };
>  
> -- 
> 2.31.1
> 

RE: [PATCH] PCI/P2PDMA: Update device table with 3rd gen Xeon platform information

[Ruhl, Michael J]

>-----Original Message-----
>From: Bjorn Helgaas <helgaas@kernel.org>
>Sent: Friday, February 25, 2022 12:10 PM
>To: Ruhl, Michael J <michael.j.ruhl@intel.com>
>Cc: linux-pci@vger.kernel.org; linux-kernel@vger.kernel.org;
>bhelgaas@google.com; logang@deltatee.com; Williams, Dan J
><dan.j.williams@intel.com>
>Subject: Re: [PATCH] PCI/P2PDMA: Update device table with 3rd gen Xeon
>platform information
>
>On Wed, Feb 09, 2022 at 11:28:01AM -0500, Michael J. Ruhl wrote:
>> In order to do P2P communication the bridge ID of the platform
>> must be in the P2P device table.
>>
>> Update the P2P device table with a device id for the 3rd Gen
>> Intel Xeon Scalable Processors.
>>
>> Reviewed-by: Dan Williams <dan.j.williams@intel.com>
>> Signed-off-by: Michael J. Ruhl <michael.j.ruhl@intel.com>
>
>Updated the commit log to match previous similar patches and applied
>as below to pci/p2pdma for v5.18, thanks!

Thank you!

>Device ID 0x09a2 doesn't appear at https://pci-ids.ucw.cz/read/PC/8086
>which means "lspci" won't be able to display a human-readable name for
>these devices.  You can easily add a name at that same URL.

I will see about getting this updated asap.

Regards,

M

>Bjorn
>
>
>  commit feaea1fe8b36 ("PCI/P2PDMA: Add Intel 3rd Gen Intel Xeon Scalable
>Processors to whitelist")
>  Author: Michael J. Ruhl <michael.j.ruhl@intel.com>
>  Date:   Wed Feb 9 11:28:01 2022 -0500
>
>    PCI/P2PDMA: Add Intel 3rd Gen Intel Xeon Scalable Processors to whitelist
>
>    In order to do P2P communication the bridge ID of the platform must be in
>    the P2P device table.
>
>    Update the P2P device table with a device ID for the 3rd Gen Intel Xeon
>    Scalable Processors.
>
>    Link: https://lore.kernel.org/r/20220209162801.7647-1-
>michael.j.ruhl@intel.com
>    Signed-off-by: Michael J. Ruhl <michael.j.ruhl@intel.com>
>    Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
>    Reviewed-by: Dan Williams <dan.j.williams@intel.com>
>
>> ---
>>  drivers/pci/p2pdma.c | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/drivers/pci/p2pdma.c b/drivers/pci/p2pdma.c
>> index 1015274bd2fe..30b1df3c9d2f 100644
>> --- a/drivers/pci/p2pdma.c
>> +++ b/drivers/pci/p2pdma.c
>> @@ -321,6 +321,7 @@ static const struct pci_p2pdma_whitelist_entry {
>>  	{PCI_VENDOR_ID_INTEL,	0x2032, 0},
>>  	{PCI_VENDOR_ID_INTEL,	0x2033, 0},
>>  	{PCI_VENDOR_ID_INTEL,	0x2020, 0},
>> +	{PCI_VENDOR_ID_INTEL,	0x09a2, 0},
>>  	{}
>>  };
>>
>> --
>> 2.31.1
>>