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Fri, 17 Oct 2025 08:24:20 -0600 Message-ID: Date: Fri, 17 Oct 2025 07:24:18 -0700 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] PCI: dwc: Fix ECAM enablement when used with vendor drivers To: Krishna Chaitanya Chundru , Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org References: <20251017-ecam_fix-v1-0-f6faa3d0edf3@oss.qualcomm.com> <20251017-ecam_fix-v1-1-f6faa3d0edf3@oss.qualcomm.com> Content-Language: en-US From: Ron Economos In-Reply-To: <20251017-ecam_fix-v1-1-f6faa3d0edf3@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - box5620.bluehost.com X-AntiAbuse: Original Domain - vger.kernel.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - w6rz.net X-BWhitelist: no X-Source-IP: 73.92.56.26 X-Source-L: No X-Exim-ID: 1v9lNU-00000002ibW-0AQJ X-Source: X-Source-Args: X-Source-Dir: X-Source-Sender: c-73-92-56-26.hsd1.ca.comcast.net ([10.0.1.116]) [73.92.56.26]:52300 X-Source-Auth: re@w6rz.net X-Email-Count: 15 X-Org: HG=bhshared;ORG=bluehost; X-Source-Cap: d3NpeHJ6bmU7d3NpeHJ6bmU7Ym94NTYyMC5ibHVlaG9zdC5jb20= X-Local-Domain: yes X-CMAE-Envelope: MS4xfFVC4WlkvoZrV8IUYRTT0Y2KMiOTYNALD5OdZX78/w1VDV3j+O1BSfa16qcCNMAMlmVPVm5ivr5B/8eJ9JAxOT+UVR9hqmyeV5vz8zXQVwO5ehBRWyjj j3OB5BrtsNxDTaOwsgz2QjQVlDo7hSjw3usK5N1N0pKaoAavT3gUoE/C/eTA5w+/IvoLRsjcGQ/kRwhIzOmJIlWpqMjYdGEyv1Y= On 10/17/25 04:40, Krishna Chaitanya Chundru wrote: > When the vendor configuration space is 256MB aligned, the DesignWare > PCIe host driver enables ECAM access and sets the DBI base to the start > of the config space. This causes vendor drivers to incorrectly program > iATU regions, as they rely on the DBI address for internal accesses. > > To fix this, avoid overwriting the DBI base when ECAM is enabled. > Instead, introduce a custom ECAM PCI ops implementation that accesses > the DBI region directly for bus 0 and uses ECAM for other buses. > > Fixes: f6fd357f7afb ("PCI: dwc: Prepare the driver for enabling ECAM mechanism using iATU 'CFG Shift Feature'") > Reported-by: Ron Economos > Closes: https://lore.kernel.org/all/eac81c57-1164-4d74-a1b4-6f353c577731@w6rz.net/ > Suggested-by: Manivannan Sadhasivam > Signed-off-by: Krishna Chaitanya Chundru > --- > drivers/pci/controller/dwc/pcie-designware-host.c | 28 +++++++++++++++++++---- > 1 file changed, 24 insertions(+), 4 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c > index 20c9333bcb1c4812e2fd96047a49944574df1e6f..e92513c5bda51bde3a7157033ddbd73afa370d78 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-host.c > +++ b/drivers/pci/controller/dwc/pcie-designware-host.c > @@ -23,6 +23,7 @@ > #include "pcie-designware.h" > > static struct pci_ops dw_pcie_ops; > +static struct pci_ops dw_pcie_ecam_ops; > static struct pci_ops dw_child_pcie_ops; > > #define DW_PCIE_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ > @@ -471,9 +472,6 @@ static int dw_pcie_create_ecam_window(struct dw_pcie_rp *pp, struct resource *re > if (IS_ERR(pp->cfg)) > return PTR_ERR(pp->cfg); > > - pci->dbi_base = pp->cfg->win; > - pci->dbi_phys_addr = res->start; > - > return 0; > } > > @@ -529,7 +527,7 @@ static int dw_pcie_host_get_resources(struct dw_pcie_rp *pp) > if (ret) > return ret; > > - pp->bridge->ops = (struct pci_ops *)&pci_generic_ecam_ops.pci_ops; > + pp->bridge->ops = &dw_pcie_ecam_ops; > pp->bridge->sysdata = pp->cfg; > pp->cfg->priv = pp; > } else { > @@ -842,12 +840,34 @@ void __iomem *dw_pcie_own_conf_map_bus(struct pci_bus *bus, unsigned int devfn, > } > EXPORT_SYMBOL_GPL(dw_pcie_own_conf_map_bus); > > +static void __iomem *dw_pcie_ecam_conf_map_bus(struct pci_bus *bus, unsigned int devfn, int where) > +{ > + struct pci_config_window *cfg = bus->sysdata; > + struct dw_pcie_rp *pp = cfg->priv; > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > + unsigned int busn = bus->number; > + > + if (busn > 0) > + return pci_ecam_map_bus(bus, devfn, where); > + > + if (PCI_SLOT(devfn) > 0) > + return NULL; > + > + return pci->dbi_base + where; > +} > + > static struct pci_ops dw_pcie_ops = { > .map_bus = dw_pcie_own_conf_map_bus, > .read = pci_generic_config_read, > .write = pci_generic_config_write, > }; > > +static struct pci_ops dw_pcie_ecam_ops = { > + .map_bus = dw_pcie_ecam_conf_map_bus, > + .read = pci_generic_config_read, > + .write = pci_generic_config_write, > +}; > + > static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp) > { > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > Works good on the SiFive FU740 controller. Tested-by: Ron Economos