From: Joao Pinto <Joao.Pinto@synopsys.com>
To: Ben Hutchings <ben@decadent.org.uk>, Bjorn Helgaas <bhelgaas@google.com>
Cc: Dan Carpenter <dan.carpenter@oracle.com>,
Jingoo Han <jingoohan1@gmail.com>,
Joao Pinto <Joao.Pinto@synopsys.com>, <linux-pci@vger.kernel.org>
Subject: Re: [PATCH] PCI: designware: Fix dw_handle_msi_irq() on 64-bit BE configs
Date: Tue, 1 Aug 2017 11:45:53 +0100 [thread overview]
Message-ID: <ceccd4e5-c5f1-9a31-dfef-b86b4587b3b6@synopsys.com> (raw)
In-Reply-To: <20170720234613.GF18698@decadent.org.uk>
Hi Ben,
Às 12:46 AM de 7/21/2017, Ben Hutchings escreveu:
> Commit 1b497e6493c4 "PCI: dwc: Fix uninitialized variable in
> dw_handle_msi_irq()" fixed one problem for 64-bit architectures but
> left another. The find_next_bit() function assumes native ordering of
> bits within each word (unsigned long), so passing a pointer to a u32
> variable will cause it to scan the following 32 bits on a 64-bit
> big-endian configuration. Alternately it could result in an alignment
> fault on some architectures.
>
> Copy the status to an unsigned long variable before using
> find_next_bit().
>
> Fixes: 1b497e6493c4 ("PCI: dwc: Fix uninitialized variable in ...")
> Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
> ---
> This is compile-tested only.
>
> Ben.
>
> drivers/pci/dwc/pcie-designware-host.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
> index d29c020da082..511fc9188f98 100644
> --- a/drivers/pci/dwc/pcie-designware-host.c
> +++ b/drivers/pci/dwc/pcie-designware-host.c
> @@ -57,6 +57,7 @@ static struct irq_chip dw_msi_irq_chip = {
> irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
> {
> u32 val;
> + unsigned long bits;
Could you please declare the variable in a ordered fashion (after "int i, pos,
irq;")? I suggest to change the variable name to "status" and val would be a
temporary variable only.
> int i, pos, irq;
> irqreturn_t ret = IRQ_NONE;
>
> @@ -65,11 +66,11 @@ irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
> &val);
> if (!val)
> continue;
> + bits = val;
>
> ret = IRQ_HANDLED;
> pos = 0;
> - while ((pos = find_next_bit((unsigned long *) &val, 32,
> - pos)) != 32) {
> + while ((pos = find_next_bit(&bits, 32, pos)) != 32) {
> irq = irq_find_mapping(pp->irq_domain, i * 32 + pos);
> dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12,
> 4, 1 << pos);
>
Thanks,
Joao
prev parent reply other threads:[~2017-08-01 10:45 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-20 23:46 [PATCH] PCI: designware: Fix dw_handle_msi_irq() on 64-bit BE configs Ben Hutchings
2017-07-21 9:07 ` Dan Carpenter
2017-08-01 10:45 ` Joao Pinto [this message]
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=ceccd4e5-c5f1-9a31-dfef-b86b4587b3b6@synopsys.com \
--to=joao.pinto@synopsys.com \
--cc=ben@decadent.org.uk \
--cc=bhelgaas@google.com \
--cc=dan.carpenter@oracle.com \
--cc=jingoohan1@gmail.com \
--cc=linux-pci@vger.kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).