[PATCH v5 0/3] PCI: dwc: Clean up iATU index mess

[PATCH v5 0/3] PCI: dwc: Clean up iATU index mess

[Niklas Cassel]

This series tries to clean up the iATU index mess, by treating
iATU indexing for outbound and inbound address translation in
a consistent way (increment the index after assignment, and only
if the function call succeeded).


Changes since v4:
-Squashed patch 1 and 2, as suggested by Damien.
-Added Cc: stable+noautosel for the ECAM patch, such that stable
 maintainers will see the dependency needed by this patch.


Link to v4:
https://lore.kernel.org/linux-pci/20260123182835.831710-6-cassel@kernel.org/

Link to v3:
https://lore.kernel.org/linux-pci/20260123093208.593506-6-cassel@kernel.org/

Link to v2:
https://lore.kernel.org/linux-pci/20260122222914.523238-6-cassel@kernel.org/

Link to v1:
https://lore.kernel.org/linux-pci/20260122145411.453291-4-cassel@kernel.org/


Krishna Chaitanya Chundru (1):
  PCI: dwc: Fix missing iATU setup when ECAM is enabled

Niklas Cassel (2):
  PCI: dwc: Fix msg_atu_index assignment
  PCI: dwc: Clean up iATU index usage in dw_pcie_iatu_setup()

 .../pci/controller/dwc/pcie-designware-host.c | 91 ++++++++++++-------
 drivers/pci/controller/dwc/pcie-designware.c  |  6 ++
 2 files changed, 62 insertions(+), 35 deletions(-)


base-commit: 0ecd890e3cf54a0586247b9a384702703277e4fd
-- 
2.52.0

[PATCH v5 1/3] PCI: dwc: Fix msg_atu_index assignment

[Niklas Cassel]

When dw_pcie_iatu_setup() configures outbound address translation for both
type PCIE_ATU_TYPE_MEM and PCIE_ATU_TYPE_IO, the iATU index to use is
incremented before calling dw_pcie_prog_outbound_atu().

However, for msg_atu_index the index is not incremented before use,
causing the iATU index to be the same as the last configured iATU index,
which means that it will incorrectly use the same iATU index that is
already in use, breaking outbound address translation.

In total there are three problems with this code:
-It assigns msg_atu_index the same index that was used for the last
 outbound address translation window, rather than incrementing the index
 before assignment.
-The index should only be incremented (and msg_atu_index assigned) if the
 use_atu_msg feature is actually requested/in use (pp->use_atu_msg is set).
-If the use_atu_msg feature is requested/in use, and there are no outbound
 iATUs available, the code should return an error, as otherwise when this
 this feature is used, it will use an iATU index that is out of bounds.

Fixes: e1a4ec1a9520 ("PCI: dwc: Add generic MSG TLP support for sending PME_Turn_Off when system suspend")
Cc: stable@vger.kernel.org
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Niklas Cassel <cassel@kernel.org>
---
 drivers/pci/controller/dwc/pcie-designware-host.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index b3d6a474fd16..d7f57d77bdf5 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -982,7 +982,14 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
 		dev_warn(pci->dev, "Ranges exceed outbound iATU size (%d)\n",
 			 pci->num_ob_windows);
 
-	pp->msg_atu_index = i;
+	if (pp->use_atu_msg) {
+		if (pci->num_ob_windows > ++i) {
+			pp->msg_atu_index = i;
+		} else {
+			dev_err(pci->dev, "Cannot add outbound window for MSG TLP\n");
+			return -ENOMEM;
+		}
+	}
 
 	i = 0;
 	resource_list_for_each_entry(entry, &pp->bridge->dma_ranges) {
-- 
2.52.0

Re: [PATCH v5 1/3] PCI: dwc: Fix msg_atu_index assignment

[Hans Zhang]

On 1/27/2026 11:10 PM, Niklas Cassel wrote:
> When dw_pcie_iatu_setup() configures outbound address translation for both
> type PCIE_ATU_TYPE_MEM and PCIE_ATU_TYPE_IO, the iATU index to use is
> incremented before calling dw_pcie_prog_outbound_atu().
> 
> However, for msg_atu_index the index is not incremented before use,
> causing the iATU index to be the same as the last configured iATU index,
> which means that it will incorrectly use the same iATU index that is
> already in use, breaking outbound address translation.
> 
> In total there are three problems with this code:
> -It assigns msg_atu_index the same index that was used for the last
>   outbound address translation window, rather than incrementing the index
>   before assignment.
> -The index should only be incremented (and msg_atu_index assigned) if the
>   use_atu_msg feature is actually requested/in use (pp->use_atu_msg is set).
> -If the use_atu_msg feature is requested/in use, and there are no outbound
>   iATUs available, the code should return an error, as otherwise when this
>   this feature is used, it will use an iATU index that is out of bounds.
> 
> Fixes: e1a4ec1a9520 ("PCI: dwc: Add generic MSG TLP support for sending PME_Turn_Off when system suspend")
> Cc: stable@vger.kernel.org
> Reviewed-by: Frank Li <Frank.Li@nxp.com>
> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
> Signed-off-by: Niklas Cassel <cassel@kernel.org>

Reviewed-by: Hans Zhang <zhanghuabing@ecosda.com>

> ---
>   drivers/pci/controller/dwc/pcie-designware-host.c | 9 ++++++++-
>   1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index b3d6a474fd16..d7f57d77bdf5 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -982,7 +982,14 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
>   		dev_warn(pci->dev, "Ranges exceed outbound iATU size (%d)\n",
>   			 pci->num_ob_windows);
>   
> -	pp->msg_atu_index = i;
> +	if (pp->use_atu_msg) {
> +		if (pci->num_ob_windows > ++i) {
> +			pp->msg_atu_index = i;
> +		} else {
> +			dev_err(pci->dev, "Cannot add outbound window for MSG TLP\n");
> +			return -ENOMEM;
> +		}
> +	}
>   
>   	i = 0;
>   	resource_list_for_each_entry(entry, &pp->bridge->dma_ranges) {

Re: [PATCH v5 1/3] PCI: dwc: Fix msg_atu_index assignment

[Damien Le Moal]

On 1/28/26 12:10 AM, Niklas Cassel wrote:
> When dw_pcie_iatu_setup() configures outbound address translation for both
> type PCIE_ATU_TYPE_MEM and PCIE_ATU_TYPE_IO, the iATU index to use is
> incremented before calling dw_pcie_prog_outbound_atu().
> 
> However, for msg_atu_index the index is not incremented before use,
> causing the iATU index to be the same as the last configured iATU index,
> which means that it will incorrectly use the same iATU index that is
> already in use, breaking outbound address translation.
> 
> In total there are three problems with this code:
> -It assigns msg_atu_index the same index that was used for the last
>  outbound address translation window, rather than incrementing the index
>  before assignment.
> -The index should only be incremented (and msg_atu_index assigned) if the
>  use_atu_msg feature is actually requested/in use (pp->use_atu_msg is set).
> -If the use_atu_msg feature is requested/in use, and there are no outbound
>  iATUs available, the code should return an error, as otherwise when this
>  this feature is used, it will use an iATU index that is out of bounds.
> 
> Fixes: e1a4ec1a9520 ("PCI: dwc: Add generic MSG TLP support for sending PME_Turn_Off when system suspend")
> Cc: stable@vger.kernel.org
> Reviewed-by: Frank Li <Frank.Li@nxp.com>
> Reviewed-by: Shawn Lin <shawn.lin@rock-chips.com>
> Signed-off-by: Niklas Cassel <cassel@kernel.org>
> ---
>  drivers/pci/controller/dwc/pcie-designware-host.c | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index b3d6a474fd16..d7f57d77bdf5 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -982,7 +982,14 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
>  		dev_warn(pci->dev, "Ranges exceed outbound iATU size (%d)\n",
>  			 pci->num_ob_windows);
>  
> -	pp->msg_atu_index = i;
> +	if (pp->use_atu_msg) {
> +		if (pci->num_ob_windows > ++i) {

I would still prefer:

		i++;
		if (pci->num_ob_windows > i) {

As that is far easier to understand rather than having to remember the value
return vs increment order for ++ as a prefix or suffix.
But not going to fight it.

Reviewed-by: Damien Le Moal <dlemoal@kernel.org>

> +			pp->msg_atu_index = i;
> +		} else {
> +			dev_err(pci->dev, "Cannot add outbound window for MSG TLP\n");
> +			return -ENOMEM;
> +		}
> +	}
>  
>  	i = 0;
>  	resource_list_for_each_entry(entry, &pp->bridge->dma_ranges) {


-- 
Damien Le Moal
Western Digital Research

Re: [PATCH v5 1/3] PCI: dwc: Fix msg_atu_index assignment

[Maciej W. Rozycki]

On Tue, 27 Jan 2026, Niklas Cassel wrote:

> When dw_pcie_iatu_setup() configures outbound address translation for both
> type PCIE_ATU_TYPE_MEM and PCIE_ATU_TYPE_IO, the iATU index to use is
> incremented before calling dw_pcie_prog_outbound_atu().

Tested-by: Maciej W. Rozycki <macro@orcam.me.uk>

-- with SiFive FU740 RISC-V SoC onboard a HiFive Unmatched system.

  Maciej

[PATCH v5 2/3] PCI: dwc: Clean up iATU index usage in dw_pcie_iatu_setup()

[Niklas Cassel]

The current iATU index usage in dw_pcie_iatu_setup() is a mess.

For outbound address translation the index is incremented before usage.
For inbound address translation the index is incremented after usage.

Incrementing the index after usage make much more sense, and make the
index usage consistent for both outbound and inbound address translation.

Most likely, the overly complicated logic for the outbound address
translation is because the iATU at index 0 is reserved for CFG IOs
(dw_pcie_other_conf_map_bus()), however, we should be able to use the
exact same logic for the indexing of the outbound and inbound iATUs.
(Only the starting index should be different.)

Create two new variables ob_iatu_index and ib_iatu_index, which makes
it more clear from the name itself that it is a zeroes based index,
and only increment the index if the iATU configuration call succeeded.

Since we always check if there is an index available immediately before
programming the iATU, we can remove the useless "ranges exceed outbound
iATU size" warnings, as the code is already unreachable. For the same
reason, we can also remove the useless breaks outside of the while loops.

No functional changes intended.

Signed-off-by: Niklas Cassel <cassel@kernel.org>
---
 .../pci/controller/dwc/pcie-designware-host.c | 59 ++++++++++---------
 1 file changed, 31 insertions(+), 28 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index d7f57d77bdf5..87e6a32dbb9a 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -892,9 +892,10 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct dw_pcie_ob_atu_cfg atu = { 0 };
 	struct resource_entry *entry;
+	int ob_iatu_index;
+	int ib_iatu_index;
 	int i, ret;
 
-	/* Note the very first outbound ATU is used for CFG IOs */
 	if (!pci->num_ob_windows) {
 		dev_err(pci->dev, "No outbound iATU found\n");
 		return -EINVAL;
@@ -910,16 +911,18 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
 	for (i = 0; i < pci->num_ib_windows; i++)
 		dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_IB, i);
 
-	i = 0;
+	/*
+	 * NOTE: For outbound address translation, outbound iATU at index 0 is
+	 * reserved for CFG IOs (dw_pcie_other_conf_map_bus()), thus start at
+	 * index 1.
+	 */
+	ob_iatu_index = 1;
 	resource_list_for_each_entry(entry, &pp->bridge->windows) {
 		resource_size_t res_size;
 
 		if (resource_type(entry->res) != IORESOURCE_MEM)
 			continue;
 
-		if (pci->num_ob_windows <= i + 1)
-			break;
-
 		atu.type = PCIE_ATU_TYPE_MEM;
 		atu.parent_bus_addr = entry->res->start - pci->parent_bus_offset;
 		atu.pci_addr = entry->res->start - entry->offset;
@@ -937,13 +940,13 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
 			 * middle. Otherwise, we would end up only partially
 			 * mapping a single resource.
 			 */
-			if (pci->num_ob_windows <= ++i) {
-				dev_err(pci->dev, "Exhausted outbound windows for region: %pr\n",
+			if (ob_iatu_index >= pci->num_ob_windows) {
+				dev_err(pci->dev, "Cannot add outbound window for region: %pr\n",
 					entry->res);
 				return -ENOMEM;
 			}
 
-			atu.index = i;
+			atu.index = ob_iatu_index;
 			atu.size = MIN(pci->region_limit + 1, res_size);
 
 			ret = dw_pcie_prog_outbound_atu(pci, &atu);
@@ -953,6 +956,7 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
 				return ret;
 			}
 
+			ob_iatu_index++;
 			atu.parent_bus_addr += atu.size;
 			atu.pci_addr += atu.size;
 			res_size -= atu.size;
@@ -960,8 +964,8 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
 	}
 
 	if (pp->io_size) {
-		if (pci->num_ob_windows > ++i) {
-			atu.index = i;
+		if (ob_iatu_index < pci->num_ob_windows) {
+			atu.index = ob_iatu_index;
 			atu.type = PCIE_ATU_TYPE_IO;
 			atu.parent_bus_addr = pp->io_base - pci->parent_bus_offset;
 			atu.pci_addr = pp->io_bus_addr;
@@ -973,34 +977,35 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
 					entry->res);
 				return ret;
 			}
+			ob_iatu_index++;
 		} else {
+			/*
+			 * If there are not enough outbound windows to give I/O
+			 * space its own iATU, the outbound iATU at index 0 will
+			 * be shared between I/O space and CFG IOs, by
+			 * temporarily reconfiguring the iATU to CFG space, in
+			 * order to do a CFG IO, and then immediately restoring
+			 * it to I/O space.
+			 */
 			pp->cfg0_io_shared = true;
 		}
 	}
 
-	if (pci->num_ob_windows <= i)
-		dev_warn(pci->dev, "Ranges exceed outbound iATU size (%d)\n",
-			 pci->num_ob_windows);
-
 	if (pp->use_atu_msg) {
-		if (pci->num_ob_windows > ++i) {
-			pp->msg_atu_index = i;
-		} else {
+		if (ob_iatu_index >= pci->num_ob_windows) {
 			dev_err(pci->dev, "Cannot add outbound window for MSG TLP\n");
 			return -ENOMEM;
 		}
+		pp->msg_atu_index = ob_iatu_index++;
 	}
 
-	i = 0;
+	ib_iatu_index = 0;
 	resource_list_for_each_entry(entry, &pp->bridge->dma_ranges) {
 		resource_size_t res_start, res_size, window_size;
 
 		if (resource_type(entry->res) != IORESOURCE_MEM)
 			continue;
 
-		if (pci->num_ib_windows <= i)
-			break;
-
 		res_size = resource_size(entry->res);
 		res_start = entry->res->start;
 		while (res_size > 0) {
@@ -1009,14 +1014,15 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
 			 * middle. Otherwise, we would end up only partially
 			 * mapping a single resource.
 			 */
-			if (pci->num_ib_windows <= i) {
-				dev_err(pci->dev, "Exhausted inbound windows for region: %pr\n",
+			if (ib_iatu_index >= pci->num_ib_windows) {
+				dev_err(pci->dev, "Cannot add inbound window for region: %pr\n",
 					entry->res);
 				return -ENOMEM;
 			}
 
 			window_size = MIN(pci->region_limit + 1, res_size);
-			ret = dw_pcie_prog_inbound_atu(pci, i++, PCIE_ATU_TYPE_MEM, res_start,
+			ret = dw_pcie_prog_inbound_atu(pci, ib_iatu_index,
+						       PCIE_ATU_TYPE_MEM, res_start,
 						       res_start - entry->offset, window_size);
 			if (ret) {
 				dev_err(pci->dev, "Failed to set DMA range %pr\n",
@@ -1024,15 +1030,12 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
 				return ret;
 			}
 
+			ib_iatu_index++;
 			res_start += window_size;
 			res_size -= window_size;
 		}
 	}
 
-	if (pci->num_ib_windows <= i)
-		dev_warn(pci->dev, "Dma-ranges exceed inbound iATU size (%u)\n",
-			 pci->num_ib_windows);
-
 	return 0;
 }
 
-- 
2.52.0

Re: [PATCH v5 2/3] PCI: dwc: Clean up iATU index usage in dw_pcie_iatu_setup()

[Frank Li]

On Tue, Jan 27, 2026 at 04:10:40PM +0100, Niklas Cassel wrote:
> The current iATU index usage in dw_pcie_iatu_setup() is a mess.
>
> For outbound address translation the index is incremented before usage.
> For inbound address translation the index is incremented after usage.
>
> Incrementing the index after usage make much more sense, and make the
> index usage consistent for both outbound and inbound address translation.
>
> Most likely, the overly complicated logic for the outbound address
> translation is because the iATU at index 0 is reserved for CFG IOs
> (dw_pcie_other_conf_map_bus()), however, we should be able to use the
> exact same logic for the indexing of the outbound and inbound iATUs.
> (Only the starting index should be different.)
>
> Create two new variables ob_iatu_index and ib_iatu_index, which makes
> it more clear from the name itself that it is a zeroes based index,
> and only increment the index if the iATU configuration call succeeded.
>
> Since we always check if there is an index available immediately before
> programming the iATU, we can remove the useless "ranges exceed outbound
> iATU size" warnings, as the code is already unreachable. For the same
> reason, we can also remove the useless breaks outside of the while loops.
>
> No functional changes intended.
>
> Signed-off-by: Niklas Cassel <cassel@kernel.org>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
>  .../pci/controller/dwc/pcie-designware-host.c | 59 ++++++++++---------
>  1 file changed, 31 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index d7f57d77bdf5..87e6a32dbb9a 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -892,9 +892,10 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
>  	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct dw_pcie_ob_atu_cfg atu = { 0 };
>  	struct resource_entry *entry;
> +	int ob_iatu_index;
> +	int ib_iatu_index;
>  	int i, ret;
>
> -	/* Note the very first outbound ATU is used for CFG IOs */
>  	if (!pci->num_ob_windows) {
>  		dev_err(pci->dev, "No outbound iATU found\n");
>  		return -EINVAL;
> @@ -910,16 +911,18 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
>  	for (i = 0; i < pci->num_ib_windows; i++)
>  		dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_IB, i);
>
> -	i = 0;
> +	/*
> +	 * NOTE: For outbound address translation, outbound iATU at index 0 is
> +	 * reserved for CFG IOs (dw_pcie_other_conf_map_bus()), thus start at
> +	 * index 1.
> +	 */
> +	ob_iatu_index = 1;
>  	resource_list_for_each_entry(entry, &pp->bridge->windows) {
>  		resource_size_t res_size;
>
>  		if (resource_type(entry->res) != IORESOURCE_MEM)
>  			continue;
>
> -		if (pci->num_ob_windows <= i + 1)
> -			break;
> -
>  		atu.type = PCIE_ATU_TYPE_MEM;
>  		atu.parent_bus_addr = entry->res->start - pci->parent_bus_offset;
>  		atu.pci_addr = entry->res->start - entry->offset;
> @@ -937,13 +940,13 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
>  			 * middle. Otherwise, we would end up only partially
>  			 * mapping a single resource.
>  			 */
> -			if (pci->num_ob_windows <= ++i) {
> -				dev_err(pci->dev, "Exhausted outbound windows for region: %pr\n",
> +			if (ob_iatu_index >= pci->num_ob_windows) {
> +				dev_err(pci->dev, "Cannot add outbound window for region: %pr\n",
>  					entry->res);
>  				return -ENOMEM;
>  			}
>
> -			atu.index = i;
> +			atu.index = ob_iatu_index;
>  			atu.size = MIN(pci->region_limit + 1, res_size);
>
>  			ret = dw_pcie_prog_outbound_atu(pci, &atu);
> @@ -953,6 +956,7 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
>  				return ret;
>  			}
>
> +			ob_iatu_index++;
>  			atu.parent_bus_addr += atu.size;
>  			atu.pci_addr += atu.size;
>  			res_size -= atu.size;
> @@ -960,8 +964,8 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
>  	}
>
>  	if (pp->io_size) {
> -		if (pci->num_ob_windows > ++i) {
> -			atu.index = i;
> +		if (ob_iatu_index < pci->num_ob_windows) {
> +			atu.index = ob_iatu_index;
>  			atu.type = PCIE_ATU_TYPE_IO;
>  			atu.parent_bus_addr = pp->io_base - pci->parent_bus_offset;
>  			atu.pci_addr = pp->io_bus_addr;
> @@ -973,34 +977,35 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
>  					entry->res);
>  				return ret;
>  			}
> +			ob_iatu_index++;
>  		} else {
> +			/*
> +			 * If there are not enough outbound windows to give I/O
> +			 * space its own iATU, the outbound iATU at index 0 will
> +			 * be shared between I/O space and CFG IOs, by
> +			 * temporarily reconfiguring the iATU to CFG space, in
> +			 * order to do a CFG IO, and then immediately restoring
> +			 * it to I/O space.
> +			 */
>  			pp->cfg0_io_shared = true;
>  		}
>  	}
>
> -	if (pci->num_ob_windows <= i)
> -		dev_warn(pci->dev, "Ranges exceed outbound iATU size (%d)\n",
> -			 pci->num_ob_windows);
> -
>  	if (pp->use_atu_msg) {
> -		if (pci->num_ob_windows > ++i) {
> -			pp->msg_atu_index = i;
> -		} else {
> +		if (ob_iatu_index >= pci->num_ob_windows) {
>  			dev_err(pci->dev, "Cannot add outbound window for MSG TLP\n");
>  			return -ENOMEM;
>  		}
> +		pp->msg_atu_index = ob_iatu_index++;
>  	}
>
> -	i = 0;
> +	ib_iatu_index = 0;
>  	resource_list_for_each_entry(entry, &pp->bridge->dma_ranges) {
>  		resource_size_t res_start, res_size, window_size;
>
>  		if (resource_type(entry->res) != IORESOURCE_MEM)
>  			continue;
>
> -		if (pci->num_ib_windows <= i)
> -			break;
> -
>  		res_size = resource_size(entry->res);
>  		res_start = entry->res->start;
>  		while (res_size > 0) {
> @@ -1009,14 +1014,15 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
>  			 * middle. Otherwise, we would end up only partially
>  			 * mapping a single resource.
>  			 */
> -			if (pci->num_ib_windows <= i) {
> -				dev_err(pci->dev, "Exhausted inbound windows for region: %pr\n",
> +			if (ib_iatu_index >= pci->num_ib_windows) {
> +				dev_err(pci->dev, "Cannot add inbound window for region: %pr\n",
>  					entry->res);
>  				return -ENOMEM;
>  			}
>
>  			window_size = MIN(pci->region_limit + 1, res_size);
> -			ret = dw_pcie_prog_inbound_atu(pci, i++, PCIE_ATU_TYPE_MEM, res_start,
> +			ret = dw_pcie_prog_inbound_atu(pci, ib_iatu_index,
> +						       PCIE_ATU_TYPE_MEM, res_start,
>  						       res_start - entry->offset, window_size);
>  			if (ret) {
>  				dev_err(pci->dev, "Failed to set DMA range %pr\n",
> @@ -1024,15 +1030,12 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
>  				return ret;
>  			}
>
> +			ib_iatu_index++;
>  			res_start += window_size;
>  			res_size -= window_size;
>  		}
>  	}
>
> -	if (pci->num_ib_windows <= i)
> -		dev_warn(pci->dev, "Dma-ranges exceed inbound iATU size (%u)\n",
> -			 pci->num_ib_windows);
> -
>  	return 0;
>  }
>
> --
> 2.52.0
>

Re: [PATCH v5 2/3] PCI: dwc: Clean up iATU index usage in dw_pcie_iatu_setup()

[Hans Zhang]

On 1/27/2026 11:10 PM, Niklas Cassel wrote:
> The current iATU index usage in dw_pcie_iatu_setup() is a mess.
> 
> For outbound address translation the index is incremented before usage.
> For inbound address translation the index is incremented after usage.
> 
> Incrementing the index after usage make much more sense, and make the
> index usage consistent for both outbound and inbound address translation.
> 
> Most likely, the overly complicated logic for the outbound address
> translation is because the iATU at index 0 is reserved for CFG IOs
> (dw_pcie_other_conf_map_bus()), however, we should be able to use the
> exact same logic for the indexing of the outbound and inbound iATUs.
> (Only the starting index should be different.)
> 
> Create two new variables ob_iatu_index and ib_iatu_index, which makes
> it more clear from the name itself that it is a zeroes based index,
> and only increment the index if the iATU configuration call succeeded.
> 
> Since we always check if there is an index available immediately before
> programming the iATU, we can remove the useless "ranges exceed outbound
> iATU size" warnings, as the code is already unreachable. For the same
> reason, we can also remove the useless breaks outside of the while loops.
> 
> No functional changes intended.
> 
> Signed-off-by: Niklas Cassel <cassel@kernel.org>

Reviewed-by: Hans Zhang <zhanghuabing@ecosda.com>

> ---
>   .../pci/controller/dwc/pcie-designware-host.c | 59 ++++++++++---------
>   1 file changed, 31 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index d7f57d77bdf5..87e6a32dbb9a 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -892,9 +892,10 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
>   	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>   	struct dw_pcie_ob_atu_cfg atu = { 0 };
>   	struct resource_entry *entry;
> +	int ob_iatu_index;
> +	int ib_iatu_index;
>   	int i, ret;
>   
> -	/* Note the very first outbound ATU is used for CFG IOs */
>   	if (!pci->num_ob_windows) {
>   		dev_err(pci->dev, "No outbound iATU found\n");
>   		return -EINVAL;
> @@ -910,16 +911,18 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
>   	for (i = 0; i < pci->num_ib_windows; i++)
>   		dw_pcie_disable_atu(pci, PCIE_ATU_REGION_DIR_IB, i);
>   
> -	i = 0;
> +	/*
> +	 * NOTE: For outbound address translation, outbound iATU at index 0 is
> +	 * reserved for CFG IOs (dw_pcie_other_conf_map_bus()), thus start at
> +	 * index 1.
> +	 */
> +	ob_iatu_index = 1;
>   	resource_list_for_each_entry(entry, &pp->bridge->windows) {
>   		resource_size_t res_size;
>   
>   		if (resource_type(entry->res) != IORESOURCE_MEM)
>   			continue;
>   
> -		if (pci->num_ob_windows <= i + 1)
> -			break;
> -
>   		atu.type = PCIE_ATU_TYPE_MEM;
>   		atu.parent_bus_addr = entry->res->start - pci->parent_bus_offset;
>   		atu.pci_addr = entry->res->start - entry->offset;
> @@ -937,13 +940,13 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
>   			 * middle. Otherwise, we would end up only partially
>   			 * mapping a single resource.
>   			 */
> -			if (pci->num_ob_windows <= ++i) {
> -				dev_err(pci->dev, "Exhausted outbound windows for region: %pr\n",
> +			if (ob_iatu_index >= pci->num_ob_windows) {
> +				dev_err(pci->dev, "Cannot add outbound window for region: %pr\n",
>   					entry->res);
>   				return -ENOMEM;
>   			}
>   
> -			atu.index = i;
> +			atu.index = ob_iatu_index;
>   			atu.size = MIN(pci->region_limit + 1, res_size);
>   
>   			ret = dw_pcie_prog_outbound_atu(pci, &atu);
> @@ -953,6 +956,7 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
>   				return ret;
>   			}
>   
> +			ob_iatu_index++;
>   			atu.parent_bus_addr += atu.size;
>   			atu.pci_addr += atu.size;
>   			res_size -= atu.size;
> @@ -960,8 +964,8 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
>   	}
>   
>   	if (pp->io_size) {
> -		if (pci->num_ob_windows > ++i) {
> -			atu.index = i;
> +		if (ob_iatu_index < pci->num_ob_windows) {
> +			atu.index = ob_iatu_index;
>   			atu.type = PCIE_ATU_TYPE_IO;
>   			atu.parent_bus_addr = pp->io_base - pci->parent_bus_offset;
>   			atu.pci_addr = pp->io_bus_addr;
> @@ -973,34 +977,35 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
>   					entry->res);
>   				return ret;
>   			}
> +			ob_iatu_index++;
>   		} else {
> +			/*
> +			 * If there are not enough outbound windows to give I/O
> +			 * space its own iATU, the outbound iATU at index 0 will
> +			 * be shared between I/O space and CFG IOs, by
> +			 * temporarily reconfiguring the iATU to CFG space, in
> +			 * order to do a CFG IO, and then immediately restoring
> +			 * it to I/O space.
> +			 */
>   			pp->cfg0_io_shared = true;
>   		}
>   	}
>   
> -	if (pci->num_ob_windows <= i)
> -		dev_warn(pci->dev, "Ranges exceed outbound iATU size (%d)\n",
> -			 pci->num_ob_windows);
> -
>   	if (pp->use_atu_msg) {
> -		if (pci->num_ob_windows > ++i) {
> -			pp->msg_atu_index = i;
> -		} else {
> +		if (ob_iatu_index >= pci->num_ob_windows) {
>   			dev_err(pci->dev, "Cannot add outbound window for MSG TLP\n");
>   			return -ENOMEM;
>   		}
> +		pp->msg_atu_index = ob_iatu_index++;
>   	}
>   
> -	i = 0;
> +	ib_iatu_index = 0;
>   	resource_list_for_each_entry(entry, &pp->bridge->dma_ranges) {
>   		resource_size_t res_start, res_size, window_size;
>   
>   		if (resource_type(entry->res) != IORESOURCE_MEM)
>   			continue;
>   
> -		if (pci->num_ib_windows <= i)
> -			break;
> -
>   		res_size = resource_size(entry->res);
>   		res_start = entry->res->start;
>   		while (res_size > 0) {
> @@ -1009,14 +1014,15 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
>   			 * middle. Otherwise, we would end up only partially
>   			 * mapping a single resource.
>   			 */
> -			if (pci->num_ib_windows <= i) {
> -				dev_err(pci->dev, "Exhausted inbound windows for region: %pr\n",
> +			if (ib_iatu_index >= pci->num_ib_windows) {
> +				dev_err(pci->dev, "Cannot add inbound window for region: %pr\n",
>   					entry->res);
>   				return -ENOMEM;
>   			}
>   
>   			window_size = MIN(pci->region_limit + 1, res_size);
> -			ret = dw_pcie_prog_inbound_atu(pci, i++, PCIE_ATU_TYPE_MEM, res_start,
> +			ret = dw_pcie_prog_inbound_atu(pci, ib_iatu_index,
> +						       PCIE_ATU_TYPE_MEM, res_start,
>   						       res_start - entry->offset, window_size);
>   			if (ret) {
>   				dev_err(pci->dev, "Failed to set DMA range %pr\n",
> @@ -1024,15 +1030,12 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
>   				return ret;
>   			}
>   
> +			ib_iatu_index++;
>   			res_start += window_size;
>   			res_size -= window_size;
>   		}
>   	}
>   
> -	if (pci->num_ib_windows <= i)
> -		dev_warn(pci->dev, "Dma-ranges exceed inbound iATU size (%u)\n",
> -			 pci->num_ib_windows);
> -
>   	return 0;
>   }
>   

Re: [PATCH v5 2/3] PCI: dwc: Clean up iATU index usage in dw_pcie_iatu_setup()

[Damien Le Moal]

On 1/28/26 12:10 AM, Niklas Cassel wrote:
> The current iATU index usage in dw_pcie_iatu_setup() is a mess.
> 
> For outbound address translation the index is incremented before usage.
> For inbound address translation the index is incremented after usage.
> 
> Incrementing the index after usage make much more sense, and make the
> index usage consistent for both outbound and inbound address translation.
> 
> Most likely, the overly complicated logic for the outbound address
> translation is because the iATU at index 0 is reserved for CFG IOs
> (dw_pcie_other_conf_map_bus()), however, we should be able to use the
> exact same logic for the indexing of the outbound and inbound iATUs.
> (Only the starting index should be different.)
> 
> Create two new variables ob_iatu_index and ib_iatu_index, which makes
> it more clear from the name itself that it is a zeroes based index,
> and only increment the index if the iATU configuration call succeeded.
> 
> Since we always check if there is an index available immediately before
> programming the iATU, we can remove the useless "ranges exceed outbound
> iATU size" warnings, as the code is already unreachable. For the same
> reason, we can also remove the useless breaks outside of the while loops.
> 
> No functional changes intended.
> 
> Signed-off-by: Niklas Cassel <cassel@kernel.org>

Looks good to me.

Reviewed-by: Damien Le Moal <dlemoal@kernel.org>

-- 
Damien Le Moal
Western Digital Research

Re: [PATCH v5 2/3] PCI: dwc: Clean up iATU index usage in dw_pcie_iatu_setup()

[Maciej W. Rozycki]

On Tue, 27 Jan 2026, Niklas Cassel wrote:

> Create two new variables ob_iatu_index and ib_iatu_index, which makes
> it more clear from the name itself that it is a zeroes based index,
> and only increment the index if the iATU configuration call succeeded.

Tested-by: Maciej W. Rozycki <macro@orcam.me.uk>

-- with SiFive FU740 RISC-V SoC onboard a HiFive Unmatched system.

  Maciej

[PATCH v5 3/3] PCI: dwc: Fix missing iATU setup when ECAM is enabled

[Niklas Cassel]

From: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>

When ECAM is enabled, the driver skipped calling dw_pcie_iatu_setup()
before configuring ECAM iATU entries. This left IO and MEM outbound
windows unprogrammed, resulting in broken IO transactions. Additionally,
dw_pcie_config_ecam_iatu() was only called during host initialization,
so ECAM-related iATU entries were not restored after suspend/resume,
leading to failures in configuration space access

To resolve these issues, the ECAM iATU configuration is moved into
dw_pcie_iatu_setup(), and dw_pcie_iatu_setup() is invoked when ECAM is
enabled.

Furthermore, error checks are added in dw_pcie_prog_outbound_atu() and
dw_pcie_prog_inbound_atu() such that an error is returned if trying to
program an iATU that is outside the number of iATUs provided by the
controller.

Fixes: f6fd357f7afb ("PCI: dwc: Prepare the driver for enabling ECAM mechanism using iATU 'CFG Shift Feature'")
Cc: stable+noautosel@kernel.org # depends on Clean up iATU index usage in dw_pcie_iatu_setup()
Reported-by: Maciej W. Rozycki <macro@orcam.me.uk>
Closes: https://lore.kernel.org/all/alpine.DEB.2.21.2511280256260.36486@angie.orcam.me.uk/
Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
Co-developed-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Niklas Cassel <cassel@kernel.org>
---
 .../pci/controller/dwc/pcie-designware-host.c | 33 ++++++++++++-------
 drivers/pci/controller/dwc/pcie-designware.c  |  6 ++++
 2 files changed, 28 insertions(+), 11 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 87e6a32dbb9a..bc2e08ec515e 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -641,14 +641,6 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
 	if (ret)
 		goto err_free_msi;
 
-	if (pp->ecam_enabled) {
-		ret = dw_pcie_config_ecam_iatu(pp);
-		if (ret) {
-			dev_err(dev, "Failed to configure iATU in ECAM mode\n");
-			goto err_free_msi;
-		}
-	}
-
 	/*
 	 * Allocate the resource for MSG TLP before programming the iATU
 	 * outbound window in dw_pcie_setup_rc(). Since the allocation depends
@@ -915,8 +907,21 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
 	 * NOTE: For outbound address translation, outbound iATU at index 0 is
 	 * reserved for CFG IOs (dw_pcie_other_conf_map_bus()), thus start at
 	 * index 1.
+	 *
+	 * If using ECAM, outbound iATU at index 0 and index 1 is reserved for
+	 * CFG IOs.
 	 */
-	ob_iatu_index = 1;
+	if (pp->ecam_enabled) {
+		ob_iatu_index = 2;
+		ret = dw_pcie_config_ecam_iatu(pp);
+		if (ret) {
+			dev_err(pci->dev, "Failed to configure iATU in ECAM mode\n");
+			return ret;
+		}
+	} else {
+		ob_iatu_index = 1;
+	}
+
 	resource_list_for_each_entry(entry, &pp->bridge->windows) {
 		resource_size_t res_size;
 
@@ -985,8 +990,14 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
 			 * be shared between I/O space and CFG IOs, by
 			 * temporarily reconfiguring the iATU to CFG space, in
 			 * order to do a CFG IO, and then immediately restoring
-			 * it to I/O space.
+			 * it to I/O space. This is only implemented when using
+			 * dw_pcie_other_conf_map_bus(), which is not the case
+			 * when using ECAM.
 			 */
+			if (pp->ecam_enabled) {
+				dev_err(pci->dev, "Cannot add outbound window for I/O\n");
+				return -ENOMEM;
+			}
 			pp->cfg0_io_shared = true;
 		}
 	}
@@ -1157,7 +1168,7 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp)
 	 * the platform uses its own address translation component rather than
 	 * ATU, so we should not program the ATU here.
 	 */
-	if (pp->bridge->child_ops == &dw_child_pcie_ops) {
+	if (pp->bridge->child_ops == &dw_child_pcie_ops || pp->ecam_enabled) {
 		ret = dw_pcie_iatu_setup(pp);
 		if (ret)
 			return ret;
diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
index 18331d9e85be..5741c09dde7f 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -532,6 +532,9 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
 	u32 retries, val;
 	u64 limit_addr;
 
+	if (atu->index >= pci->num_ob_windows)
+		return -ENOSPC;
+
 	limit_addr = parent_bus_addr + atu->size - 1;
 
 	if ((limit_addr & ~pci->region_limit) != (parent_bus_addr & ~pci->region_limit) ||
@@ -605,6 +608,9 @@ int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type,
 	u64 limit_addr = pci_addr + size - 1;
 	u32 retries, val;
 
+	if (index >= pci->num_ib_windows)
+		return -ENOSPC;
+
 	if ((limit_addr & ~pci->region_limit) != (pci_addr & ~pci->region_limit) ||
 	    !IS_ALIGNED(parent_bus_addr, pci->region_align) ||
 	    !IS_ALIGNED(pci_addr, pci->region_align) || !size) {
-- 
2.52.0

Re: [PATCH v5 3/3] PCI: dwc: Fix missing iATU setup when ECAM is enabled

[Frank Li]

On Tue, Jan 27, 2026 at 04:10:41PM +0100, Niklas Cassel wrote:
> From: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
>
> When ECAM is enabled, the driver skipped calling dw_pcie_iatu_setup()
> before configuring ECAM iATU entries. This left IO and MEM outbound
> windows unprogrammed, resulting in broken IO transactions. Additionally,
> dw_pcie_config_ecam_iatu() was only called during host initialization,
> so ECAM-related iATU entries were not restored after suspend/resume,
> leading to failures in configuration space access
>
> To resolve these issues, the ECAM iATU configuration is moved into
> dw_pcie_iatu_setup(), and dw_pcie_iatu_setup() is invoked when ECAM is
> enabled.
>
> Furthermore, error checks are added in dw_pcie_prog_outbound_atu() and
> dw_pcie_prog_inbound_atu() such that an error is returned if trying to
> program an iATU that is outside the number of iATUs provided by the
> controller.
>
> Fixes: f6fd357f7afb ("PCI: dwc: Prepare the driver for enabling ECAM mechanism using iATU 'CFG Shift Feature'")
> Cc: stable+noautosel@kernel.org # depends on Clean up iATU index usage in dw_pcie_iatu_setup()
> Reported-by: Maciej W. Rozycki <macro@orcam.me.uk>
> Closes: https://lore.kernel.org/all/alpine.DEB.2.21.2511280256260.36486@angie.orcam.me.uk/
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> Co-developed-by: Niklas Cassel <cassel@kernel.org>
> Signed-off-by: Niklas Cassel <cassel@kernel.org>
> ---
Reviewed-by: Frank Li <Frank.Li@nxp.com>
>  .../pci/controller/dwc/pcie-designware-host.c | 33 ++++++++++++-------
>  drivers/pci/controller/dwc/pcie-designware.c  |  6 ++++
>  2 files changed, 28 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 87e6a32dbb9a..bc2e08ec515e 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -641,14 +641,6 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
>  	if (ret)
>  		goto err_free_msi;
>
> -	if (pp->ecam_enabled) {
> -		ret = dw_pcie_config_ecam_iatu(pp);
> -		if (ret) {
> -			dev_err(dev, "Failed to configure iATU in ECAM mode\n");
> -			goto err_free_msi;
> -		}
> -	}
> -
>  	/*
>  	 * Allocate the resource for MSG TLP before programming the iATU
>  	 * outbound window in dw_pcie_setup_rc(). Since the allocation depends
> @@ -915,8 +907,21 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
>  	 * NOTE: For outbound address translation, outbound iATU at index 0 is
>  	 * reserved for CFG IOs (dw_pcie_other_conf_map_bus()), thus start at
>  	 * index 1.
> +	 *
> +	 * If using ECAM, outbound iATU at index 0 and index 1 is reserved for
> +	 * CFG IOs.
>  	 */
> -	ob_iatu_index = 1;
> +	if (pp->ecam_enabled) {
> +		ob_iatu_index = 2;
> +		ret = dw_pcie_config_ecam_iatu(pp);
> +		if (ret) {
> +			dev_err(pci->dev, "Failed to configure iATU in ECAM mode\n");
> +			return ret;
> +		}
> +	} else {
> +		ob_iatu_index = 1;
> +	}
> +
>  	resource_list_for_each_entry(entry, &pp->bridge->windows) {
>  		resource_size_t res_size;
>
> @@ -985,8 +990,14 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
>  			 * be shared between I/O space and CFG IOs, by
>  			 * temporarily reconfiguring the iATU to CFG space, in
>  			 * order to do a CFG IO, and then immediately restoring
> -			 * it to I/O space.
> +			 * it to I/O space. This is only implemented when using
> +			 * dw_pcie_other_conf_map_bus(), which is not the case
> +			 * when using ECAM.
>  			 */
> +			if (pp->ecam_enabled) {
> +				dev_err(pci->dev, "Cannot add outbound window for I/O\n");
> +				return -ENOMEM;
> +			}
>  			pp->cfg0_io_shared = true;
>  		}
>  	}
> @@ -1157,7 +1168,7 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp)
>  	 * the platform uses its own address translation component rather than
>  	 * ATU, so we should not program the ATU here.
>  	 */
> -	if (pp->bridge->child_ops == &dw_child_pcie_ops) {
> +	if (pp->bridge->child_ops == &dw_child_pcie_ops || pp->ecam_enabled) {
>  		ret = dw_pcie_iatu_setup(pp);
>  		if (ret)
>  			return ret;
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 18331d9e85be..5741c09dde7f 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -532,6 +532,9 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
>  	u32 retries, val;
>  	u64 limit_addr;
>
> +	if (atu->index >= pci->num_ob_windows)
> +		return -ENOSPC;
> +
>  	limit_addr = parent_bus_addr + atu->size - 1;
>
>  	if ((limit_addr & ~pci->region_limit) != (parent_bus_addr & ~pci->region_limit) ||
> @@ -605,6 +608,9 @@ int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type,
>  	u64 limit_addr = pci_addr + size - 1;
>  	u32 retries, val;
>
> +	if (index >= pci->num_ib_windows)
> +		return -ENOSPC;
> +
>  	if ((limit_addr & ~pci->region_limit) != (pci_addr & ~pci->region_limit) ||
>  	    !IS_ALIGNED(parent_bus_addr, pci->region_align) ||
>  	    !IS_ALIGNED(pci_addr, pci->region_align) || !size) {
> --
> 2.52.0
>

Re: [PATCH v5 3/3] PCI: dwc: Fix missing iATU setup when ECAM is enabled

[Hans Zhang]

On 1/27/2026 11:10 PM, Niklas Cassel wrote:
> From: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> 
> When ECAM is enabled, the driver skipped calling dw_pcie_iatu_setup()
> before configuring ECAM iATU entries. This left IO and MEM outbound
> windows unprogrammed, resulting in broken IO transactions. Additionally,
> dw_pcie_config_ecam_iatu() was only called during host initialization,
> so ECAM-related iATU entries were not restored after suspend/resume,
> leading to failures in configuration space access
> 
> To resolve these issues, the ECAM iATU configuration is moved into
> dw_pcie_iatu_setup(), and dw_pcie_iatu_setup() is invoked when ECAM is
> enabled.
> 
> Furthermore, error checks are added in dw_pcie_prog_outbound_atu() and
> dw_pcie_prog_inbound_atu() such that an error is returned if trying to
> program an iATU that is outside the number of iATUs provided by the
> controller.
> 
> Fixes: f6fd357f7afb ("PCI: dwc: Prepare the driver for enabling ECAM mechanism using iATU 'CFG Shift Feature'")
> Cc: stable+noautosel@kernel.org # depends on Clean up iATU index usage in dw_pcie_iatu_setup()
> Reported-by: Maciej W. Rozycki <macro@orcam.me.uk>
> Closes: https://lore.kernel.org/all/alpine.DEB.2.21.2511280256260.36486@angie.orcam.me.uk/
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> Co-developed-by: Niklas Cassel <cassel@kernel.org>
> Signed-off-by: Niklas Cassel <cassel@kernel.org>

Reviewed-by: Hans Zhang <zhanghuabing@ecosda.com>

> ---
>   .../pci/controller/dwc/pcie-designware-host.c | 33 ++++++++++++-------
>   drivers/pci/controller/dwc/pcie-designware.c  |  6 ++++
>   2 files changed, 28 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 87e6a32dbb9a..bc2e08ec515e 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -641,14 +641,6 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)
>   	if (ret)
>   		goto err_free_msi;
>   
> -	if (pp->ecam_enabled) {
> -		ret = dw_pcie_config_ecam_iatu(pp);
> -		if (ret) {
> -			dev_err(dev, "Failed to configure iATU in ECAM mode\n");
> -			goto err_free_msi;
> -		}
> -	}
> -
>   	/*
>   	 * Allocate the resource for MSG TLP before programming the iATU
>   	 * outbound window in dw_pcie_setup_rc(). Since the allocation depends
> @@ -915,8 +907,21 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
>   	 * NOTE: For outbound address translation, outbound iATU at index 0 is
>   	 * reserved for CFG IOs (dw_pcie_other_conf_map_bus()), thus start at
>   	 * index 1.
> +	 *
> +	 * If using ECAM, outbound iATU at index 0 and index 1 is reserved for
> +	 * CFG IOs.
>   	 */
> -	ob_iatu_index = 1;
> +	if (pp->ecam_enabled) {
> +		ob_iatu_index = 2;
> +		ret = dw_pcie_config_ecam_iatu(pp);
> +		if (ret) {
> +			dev_err(pci->dev, "Failed to configure iATU in ECAM mode\n");
> +			return ret;
> +		}
> +	} else {
> +		ob_iatu_index = 1;
> +	}
> +
>   	resource_list_for_each_entry(entry, &pp->bridge->windows) {
>   		resource_size_t res_size;
>   
> @@ -985,8 +990,14 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
>   			 * be shared between I/O space and CFG IOs, by
>   			 * temporarily reconfiguring the iATU to CFG space, in
>   			 * order to do a CFG IO, and then immediately restoring
> -			 * it to I/O space.
> +			 * it to I/O space. This is only implemented when using
> +			 * dw_pcie_other_conf_map_bus(), which is not the case
> +			 * when using ECAM.
>   			 */
> +			if (pp->ecam_enabled) {
> +				dev_err(pci->dev, "Cannot add outbound window for I/O\n");
> +				return -ENOMEM;
> +			}
>   			pp->cfg0_io_shared = true;
>   		}
>   	}
> @@ -1157,7 +1168,7 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp)
>   	 * the platform uses its own address translation component rather than
>   	 * ATU, so we should not program the ATU here.
>   	 */
> -	if (pp->bridge->child_ops == &dw_child_pcie_ops) {
> +	if (pp->bridge->child_ops == &dw_child_pcie_ops || pp->ecam_enabled) {
>   		ret = dw_pcie_iatu_setup(pp);
>   		if (ret)
>   			return ret;
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index 18331d9e85be..5741c09dde7f 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -532,6 +532,9 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci,
>   	u32 retries, val;
>   	u64 limit_addr;
>   
> +	if (atu->index >= pci->num_ob_windows)
> +		return -ENOSPC;
> +
>   	limit_addr = parent_bus_addr + atu->size - 1;
>   
>   	if ((limit_addr & ~pci->region_limit) != (parent_bus_addr & ~pci->region_limit) ||
> @@ -605,6 +608,9 @@ int dw_pcie_prog_inbound_atu(struct dw_pcie *pci, int index, int type,
>   	u64 limit_addr = pci_addr + size - 1;
>   	u32 retries, val;
>   
> +	if (index >= pci->num_ib_windows)
> +		return -ENOSPC;
> +
>   	if ((limit_addr & ~pci->region_limit) != (pci_addr & ~pci->region_limit) ||
>   	    !IS_ALIGNED(parent_bus_addr, pci->region_align) ||
>   	    !IS_ALIGNED(pci_addr, pci->region_align) || !size) {

Re: [PATCH v5 3/3] PCI: dwc: Fix missing iATU setup when ECAM is enabled

[Damien Le Moal]

On 1/28/26 12:10 AM, Niklas Cassel wrote:
> From: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> 
> When ECAM is enabled, the driver skipped calling dw_pcie_iatu_setup()
> before configuring ECAM iATU entries. This left IO and MEM outbound
> windows unprogrammed, resulting in broken IO transactions. Additionally,
> dw_pcie_config_ecam_iatu() was only called during host initialization,
> so ECAM-related iATU entries were not restored after suspend/resume,
> leading to failures in configuration space access
> 
> To resolve these issues, the ECAM iATU configuration is moved into
> dw_pcie_iatu_setup(), and dw_pcie_iatu_setup() is invoked when ECAM is
> enabled.
> 
> Furthermore, error checks are added in dw_pcie_prog_outbound_atu() and
> dw_pcie_prog_inbound_atu() such that an error is returned if trying to
> program an iATU that is outside the number of iATUs provided by the
> controller.
> 
> Fixes: f6fd357f7afb ("PCI: dwc: Prepare the driver for enabling ECAM mechanism using iATU 'CFG Shift Feature'")
> Cc: stable+noautosel@kernel.org # depends on Clean up iATU index usage in dw_pcie_iatu_setup()
> Reported-by: Maciej W. Rozycki <macro@orcam.me.uk>
> Closes: https://lore.kernel.org/all/alpine.DEB.2.21.2511280256260.36486@angie.orcam.me.uk/
> Signed-off-by: Krishna Chaitanya Chundru <krishna.chundru@oss.qualcomm.com>
> Co-developed-by: Niklas Cassel <cassel@kernel.org>
> Signed-off-by: Niklas Cassel <cassel@kernel.org>

Looks OK to me.
(one nit below)

Reviewed-by: Damien Le Moal <dlemoal@kernel.org>



> @@ -915,8 +907,21 @@ static int dw_pcie_iatu_setup(struct dw_pcie_rp *pp)
>  	 * NOTE: For outbound address translation, outbound iATU at index 0 is
>  	 * reserved for CFG IOs (dw_pcie_other_conf_map_bus()), thus start at
>  	 * index 1.
> +	 *
> +	 * If using ECAM, outbound iATU at index 0 and index 1 is reserved for

s/is/are

> +	 * CFG IOs.
>  	 */
> -	ob_iatu_index = 1;
> +	if (pp->ecam_enabled) {
> +		ob_iatu_index = 2;
> +		ret = dw_pcie_config_ecam_iatu(pp);
> +		if (ret) {
> +			dev_err(pci->dev, "Failed to configure iATU in ECAM mode\n");
> +			return ret;
> +		}
> +	} else {
> +		ob_iatu_index = 1;
> +	}
> +
>  	resource_list_for_each_entry(entry, &pp->bridge->windows) {
>  		resource_size_t res_size;



-- 
Damien Le Moal
Western Digital Research

Re: [PATCH v5 3/3] PCI: dwc: Fix missing iATU setup when ECAM is enabled

[Maciej W. Rozycki]

On Tue, 27 Jan 2026, Niklas Cassel wrote:

> To resolve these issues, the ECAM iATU configuration is moved into
> dw_pcie_iatu_setup(), and dw_pcie_iatu_setup() is invoked when ECAM is
> enabled.

Tested-by: Maciej W. Rozycki <macro@orcam.me.uk>

-- with SiFive FU740 RISC-V SoC onboard a HiFive Unmatched system.

  Maciej

Re: [PATCH v5 0/3] PCI: dwc: Clean up iATU index mess

[Manivannan Sadhasivam]

On Tue, Jan 27, 2026 at 04:10:38PM +0100, Niklas Cassel wrote:
> This series tries to clean up the iATU index mess, by treating
> iATU indexing for outbound and inbound address translation in
> a consistent way (increment the index after assignment, and only
> if the function call succeeded).
> 

Series looks good to me. However, I'd prefer waiting for Maciej's testing before
merging.

- Mani

> 
> Changes since v4:
> -Squashed patch 1 and 2, as suggested by Damien.
> -Added Cc: stable+noautosel for the ECAM patch, such that stable
>  maintainers will see the dependency needed by this patch.
> 
> 
> Link to v4:
> https://lore.kernel.org/linux-pci/20260123182835.831710-6-cassel@kernel.org/
> 
> Link to v3:
> https://lore.kernel.org/linux-pci/20260123093208.593506-6-cassel@kernel.org/
> 
> Link to v2:
> https://lore.kernel.org/linux-pci/20260122222914.523238-6-cassel@kernel.org/
> 
> Link to v1:
> https://lore.kernel.org/linux-pci/20260122145411.453291-4-cassel@kernel.org/
> 
> 
> Krishna Chaitanya Chundru (1):
>   PCI: dwc: Fix missing iATU setup when ECAM is enabled
> 
> Niklas Cassel (2):
>   PCI: dwc: Fix msg_atu_index assignment
>   PCI: dwc: Clean up iATU index usage in dw_pcie_iatu_setup()
> 
>  .../pci/controller/dwc/pcie-designware-host.c | 91 ++++++++++++-------
>  drivers/pci/controller/dwc/pcie-designware.c  |  6 ++
>  2 files changed, 62 insertions(+), 35 deletions(-)
> 
> 
> base-commit: 0ecd890e3cf54a0586247b9a384702703277e4fd
> -- 
> 2.52.0
> 

-- 
மணிவண்ணன் சதாசிவம்

Re: [PATCH v5 0/3] PCI: dwc: Clean up iATU index mess

[Niklas Cassel]

On Wed, Jan 28, 2026 at 01:32:04PM +0530, Manivannan Sadhasivam wrote:
> On Tue, Jan 27, 2026 at 04:10:38PM +0100, Niklas Cassel wrote:
> > This series tries to clean up the iATU index mess, by treating
> > iATU indexing for outbound and inbound address translation in
> > a consistent way (increment the index after assignment, and only
> > if the function call succeeded).
> > 
> 
> Series looks good to me. However, I'd prefer waiting for Maciej's testing before
> merging.

Maciej,

Any chance to get a Tested-by?

6.19-rc8 is already out.

Even if they are fixes, it would be nice if it they could make it for 7.0.


Kind regards,
Niklas

Re: [PATCH v5 0/3] PCI: dwc: Clean up iATU index mess

[Maciej W. Rozycki]

On Mon, 2 Feb 2026, Niklas Cassel wrote:

> > Series looks good to me. However, I'd prefer waiting for Maciej's testing before
> > merging.
> 
> Maciej,
> 
> Any chance to get a Tested-by?
> 
> 6.19-rc8 is already out.
> 
> Even if they are fixes, it would be nice if it they could make it for 7.0.

 Hectic time here.  I've verified it now using the system I've originally 
encountered the regression with.  No significant change in the kernel log 
compared to the previous fix by Krishna, except for different IRQ numbers 
assigned to devices (but that I reckon could be something else present in 
the pci tree that isn't there in Linus's master), and the system seems to 
boot correctly, so I do hope all is in order.

  Maciej

Re: [PATCH v5 0/3] PCI: dwc: Clean up iATU index mess

[Niklas Cassel]

On Wed, Feb 04, 2026 at 04:13:05PM +0000, Maciej W. Rozycki wrote:
> On Mon, 2 Feb 2026, Niklas Cassel wrote:
> 
> > > Series looks good to me. However, I'd prefer waiting for Maciej's testing before
> > > merging.
> > 
> > Maciej,
> > 
> > Any chance to get a Tested-by?
> > 
> > 6.19-rc8 is already out.
> > 
> > Even if they are fixes, it would be nice if it they could make it for 7.0.
> 
>  Hectic time here.  I've verified it now using the system I've originally 
> encountered the regression with.  No significant change in the kernel log 
> compared to the previous fix by Krishna, except for different IRQ numbers 
> assigned to devices (but that I reckon could be something else present in 
> the pci tree that isn't there in Linus's master), and the system seems to 
> boot correctly, so I do hope all is in order.

Thank you for testing!

Considering that it is fixes, I suggest that we queue it up for 6.20 / 7.0,
even though it will not have time to be in linux-next for a week.

(The requirement to spend time in linux-next is for new stuff, not for fixes.)


Kind regards,
Niklas

Re: [PATCH v5 0/3] PCI: dwc: Clean up iATU index mess

[Manivannan Sadhasivam]

On Tue, 27 Jan 2026 16:10:38 +0100, Niklas Cassel wrote:
> This series tries to clean up the iATU index mess, by treating
> iATU indexing for outbound and inbound address translation in
> a consistent way (increment the index after assignment, and only
> if the function call succeeded).
> 
> 
> Changes since v4:
> -Squashed patch 1 and 2, as suggested by Damien.
> -Added Cc: stable+noautosel for the ECAM patch, such that stable
>  maintainers will see the dependency needed by this patch.
> 
> [...]

Applied, thanks!

[1/3] PCI: dwc: Fix msg_atu_index assignment
      commit: 58fbf08935d9c4396417e5887df89a4e681fa7e3
[2/3] PCI: dwc: Clean up iATU index usage in dw_pcie_iatu_setup()
      commit: b5dab9b38da0a05949458276dde9227c38aa1b39
[3/3] PCI: dwc: Fix missing iATU setup when ECAM is enabled
      commit: 43d324eeb08c3dd9fff7eb9a2c617afd3b96e65c

Best regards,
-- 
Manivannan Sadhasivam <mani@kernel.org>

Re: [PATCH v5 0/3] PCI: dwc: Clean up iATU index mess

[Niklas Cassel]

On Thu, Feb 05, 2026 at 06:26:51PM +0530, Manivannan Sadhasivam wrote:
> 
> On Tue, 27 Jan 2026 16:10:38 +0100, Niklas Cassel wrote:
> > This series tries to clean up the iATU index mess, by treating
> > iATU indexing for outbound and inbound address translation in
> > a consistent way (increment the index after assignment, and only
> > if the function call succeeded).
> > 
> > 
> > Changes since v4:
> > -Squashed patch 1 and 2, as suggested by Damien.
> > -Added Cc: stable+noautosel for the ECAM patch, such that stable
> >  maintainers will see the dependency needed by this patch.
> > 
> > [...]
> 
> Applied, thanks!
> 
> [1/3] PCI: dwc: Fix msg_atu_index assignment
>       commit: 58fbf08935d9c4396417e5887df89a4e681fa7e3
> [2/3] PCI: dwc: Clean up iATU index usage in dw_pcie_iatu_setup()
>       commit: b5dab9b38da0a05949458276dde9227c38aa1b39
> [3/3] PCI: dwc: Fix missing iATU setup when ECAM is enabled
>       commit: 43d324eeb08c3dd9fff7eb9a2c617afd3b96e65c
> 
> Best regards,
> -- 
> Manivannan Sadhasivam <mani@kernel.org>
> 

Thank you Mani!

If possible, I think it would be nice if we could get:
https://lore.kernel.org/linux-pci/20260202145407.503348-1-den@valinux.co.jp/T/#t

Since it is fixing some minor things with the new feature inbound subrange
mappings.

You can probably even squash it if that is preferred.
Although, if you squash merge it,

this commit


commit 72cb5ed2a5c6d87f71a409347f7d3b228fee6bee
Author: Aksh Garg <a-garg7@ti.com>
Date:   Fri Jan 30 17:25:15 2026 +0530

    PCI: dwc: ep: Add per-PF BAR and inbound ATU mapping support

    (...)
    
    Fixes: 24ede430fa49 ("PCI: designware-ep: Add multiple PFs support for DWC")
    Fixes: cc839bef7727 ("PCI: dwc: ep: Support BAR subrange inbound mapping via Address Match Mode iATU")


has a Fixes that that references the commit that adds subrange inbound
mapping. (So if you squash merge it, you probably want to update the Fixes tag too.)


Kind regards,
Niklas