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From: Chen Wang <unicornxw@gmail.com>
To: kw@linux.com, u.kleine-koenig@baylibre.com,
	aou@eecs.berkeley.edu, arnd@arndb.de, bhelgaas@google.com,
	unicorn_wang@outlook.com, conor+dt@kernel.org, guoren@kernel.org,
	inochiama@outlook.com, krzk+dt@kernel.org, lee@kernel.org,
	lpieralisi@kernel.org, manivannan.sadhasivam@linaro.org,
	palmer@dabbelt.com, paul.walmsley@sifive.com,
	pbrobinson@gmail.com, robh@kernel.org,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-pci@vger.kernel.org, linux-riscv@lists.infradead.org,
	chao.wei@sophgo.com, xiaoguang.xing@sophgo.com,
	fengchun.li@sophgo.com
Subject: [PATCH 0/5] Add PCIe support to Sophgo SG2042 SoC
Date: Mon, 11 Nov 2024 13:59:17 +0800	[thread overview]
Message-ID: <cover.1731303328.git.unicorn_wang@outlook.com> (raw)

From: Chen Wang <unicorn_wang@outlook.com>

Sophgo's SG2042 SoC uses Cadence PCIe core to implement RC mode.

SG2042 PCIe controller supports two ways to report MSI:

Method A, the PICe controller implements an MSI interrupt controller
inside, and connect to PLIC upward through one interrupt line. Provides
memory-mapped msi address, and by programming the upper 32 bits of the
address to zero, it can be compatible with old pcie devices that only
support 32-bit msi address.

Method B, the PICe controller connects to PLIC upward through an
independent MSI controller "sophgo,sg2042-msi" on the SOC. The MSI
controller provides multiple(up to 32) interrupt sources to PLIC.
Compared with the first method, the advantage is that the interrupt
source is expanded, but because for SG2042, the msi address provided
by the MSI controller is fixed and only supports 64-bit address(> 2^32),
it is not compatible with old pcie devices that only support 32-bit
msi address.

This patchset depends on another patchset for the SG2042 MSI controller[msi].
If you need to test the DTS part, you need to apply the corresponding
patchset.

Link: https://lore.kernel.org/linux-riscv/cover.1731296803.git.unicorn_wang@outlook.com/ [msi]

Thanks,
Chen

Chen Wang (5):
  dt-bindings: pci: Add Sophgo SG2042 PCIe host
  PCI: sg2042: Add Sophgo SG2042 PCIe driver
  dt-bindings: mfd: syscon: Add sg2042 pcie ctrl compatible
  riscv: sophgo: dts: add pcie controllers for SG2042
  riscv: sophgo: dts: enable pcie for PioneerBox

 .../devicetree/bindings/mfd/syscon.yaml       |   2 +
 .../bindings/pci/sophgo,sg2042-pcie-host.yaml |  88 +++
 .../boot/dts/sophgo/sg2042-milkv-pioneer.dts  |  12 +
 arch/riscv/boot/dts/sophgo/sg2042.dtsi        |  82 +++
 drivers/pci/controller/cadence/Kconfig        |  11 +
 drivers/pci/controller/cadence/Makefile       |   1 +
 drivers/pci/controller/cadence/pcie-sg2042.c  | 611 ++++++++++++++++++
 7 files changed, 807 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
 create mode 100644 drivers/pci/controller/cadence/pcie-sg2042.c


base-commit: 2d5404caa8c7bb5c4e0435f94b28834ae5456623
-- 
2.34.1


             reply	other threads:[~2024-11-11  5:59 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-11  5:59 Chen Wang [this message]
2024-11-11  5:59 ` [PATCH 1/5] dt-bindings: pci: Add Sophgo SG2042 PCIe host Chen Wang
2024-11-12 15:59   ` Rob Herring
2024-11-14  2:51     ` Chen Wang
2024-11-11  5:59 ` [PATCH 2/5] PCI: sg2042: Add Sophgo SG2042 PCIe driver Chen Wang
2024-11-11 11:29   ` kernel test robot
2024-11-12 21:20   ` Bjorn Helgaas
2024-11-29  9:51     ` Chen Wang
2024-11-29 19:50       ` Bjorn Helgaas
2024-12-02  1:13         ` Chen Wang
2024-11-11  6:00 ` [PATCH 3/5] dt-bindings: mfd: syscon: Add sg2042 pcie ctrl compatible Chen Wang
2024-11-12 15:59   ` Rob Herring (Arm)
2024-11-11  6:00 ` [PATCH 4/5] riscv: sophgo: dts: add pcie controllers for SG2042 Chen Wang
2024-11-11  6:00 ` [PATCH 5/5] riscv: sophgo: dts: enable pcie for PioneerBox Chen Wang
  -- strict thread matches above, loose matches on Subject: below --
2025-08-28  2:15 [PATCH 0/5] Add PCIe support to Sophgo SG2042 SoC Chen Wang

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