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Wed, 27 Aug 2025 19:16:09 -0700 (PDT) Received: from localhost.localdomain ([122.8.183.87]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7450e474c97sm3505230a34.23.2025.08.27.19.16.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 27 Aug 2025 19:16:08 -0700 (PDT) From: Chen Wang To: kwilczynski@kernel.org, u.kleine-koenig@baylibre.com, aou@eecs.berkeley.edu, alex@ghiti.fr, arnd@arndb.de, bwawrzyn@cisco.com, bhelgaas@google.com, unicorn_wang@outlook.com, conor+dt@kernel.org, 18255117159@163.com, inochiama@gmail.com, kishon@kernel.org, krzk+dt@kernel.org, lpieralisi@kernel.org, mani@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh@kernel.org, s-vadapalli@ti.com, tglx@linutronix.de, thomas.richard@bootlin.com, sycamoremoon376@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-riscv@lists.infradead.org, sophgo@lists.linux.dev, rabenda.cn@gmail.com, chao.wei@sophgo.com, xiaoguang.xing@sophgo.com, fengchun.li@sophgo.com Subject: [PATCH 0/5] Add PCIe support to Sophgo SG2042 SoC Date: Thu, 28 Aug 2025 10:15:58 +0800 Message-Id: X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Chen Wang Sophgo's SG2042 SoC uses Cadence PCIe core to implement RC mode. This is a completely rewritten PCIe driver for SG2042. It inherits some previously submitted patch codes (not merged into the upstream mainline), but the biggest difference is that the support for compatibility with old 32-bit PCIe devices has been removed in this new version. This is because after discussing with community users, we felt that there was not much demand for support for old devices, so we made a new design based on the simplified design and practical needs. If someone really needs to play with old devices, we can provide them with some necessary hack patches in the downstream repository. Since the new design is quite different from the old code, I will release it as a new patch series. The old patch series can be found in here [old-series]. Note, regarding [2/5] of this patchset, this fix is introduced because the pcie->ops pointer is not filled in SG2042 PCIe driver. This is not a must-have parameter, if we use it w/o checking will cause a null pointer access error during runtime. Link: https://lore.kernel.org/linux-riscv/cover.1736923025.git.unicorn_wang@outlook.com/ [old-series] This patchset is based on v6.17-rc1. Thanks, Chen --- Chen Wang (5): dt-bindings: pci: Add Sophgo SG2042 PCIe host PCI: cadence: Fix NULL pointer error for ops PCI: sg2042: Add Sophgo SG2042 PCIe driver riscv: sophgo: dts: add pcie controllers for SG2042 riscv: sophgo: dts: enable pcie for PioneerBox .../bindings/pci/sophgo,sg2042-pcie-host.yaml | 66 +++++++++ .../boot/dts/sophgo/sg2042-milkv-pioneer.dts | 12 ++ arch/riscv/boot/dts/sophgo/sg2042.dtsi | 66 +++++++++ drivers/pci/controller/cadence/Kconfig | 12 ++ drivers/pci/controller/cadence/Makefile | 1 + .../controller/cadence/pcie-cadence-host.c | 2 +- drivers/pci/controller/cadence/pcie-cadence.c | 4 +- drivers/pci/controller/cadence/pcie-cadence.h | 6 +- drivers/pci/controller/cadence/pcie-sg2042.c | 134 ++++++++++++++++++ 9 files changed, 297 insertions(+), 6 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml create mode 100644 drivers/pci/controller/cadence/pcie-sg2042.c base-commit: 8f5ae30d69d7543eee0d70083daf4de8fe15d585 -- 2.34.1