From: Geraldo Nascimento <geraldogabriel@gmail.com>
To: linux-rockchip@lists.infradead.org
Cc: "Shawn Lin" <shawn.lin@rock-chips.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Heiko Stuebner" <heiko@sntech.de>,
"Vinod Koul" <vkoul@kernel.org>,
"Kishon Vijay Abraham I" <kishon@kernel.org>,
"Rick wertenbroek" <rick.wertenbroek@gmail.com>,
"Neil Armstrong" <neil.armstrong@linaro.org>,
"Valmantas Paliksa" <walmis@gmail.com>,
linux-phy@lists.infradead.org, linux-pci@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [RESEND PATCH v9 4/4] phy: rockchip-pcie: Properly disable TEST_WRITE strobe signal
Date: Mon, 30 Jun 2025 19:25:28 -0300 [thread overview]
Message-ID: <d514d5d5627680caafa8b7548cbdfee4307f5440.1751322015.git.geraldogabriel@gmail.com> (raw)
In-Reply-To: <cover.1751322015.git.geraldogabriel@gmail.com>
pcie_conf is used to touch TEST_WRITE strobe signal. This signal should
be enabled, a little time waited, and then disabled. Current code clearly
was copy-pasted and never disables the strobe signal. Adjust the define.
While at it, remove PHY_CFG_RD_MASK which has been unused since
64cdc0360811 ("phy: rockchip-pcie: remove unused phy_rd_cfg function").
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Geraldo Nascimento <geraldogabriel@gmail.com>
---
drivers/phy/rockchip/phy-rockchip-pcie.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/phy/rockchip/phy-rockchip-pcie.c b/drivers/phy/rockchip/phy-rockchip-pcie.c
index f22ffb41cdc2..4e2dfd01adf2 100644
--- a/drivers/phy/rockchip/phy-rockchip-pcie.c
+++ b/drivers/phy/rockchip/phy-rockchip-pcie.c
@@ -30,9 +30,8 @@
#define PHY_CFG_ADDR_SHIFT 1
#define PHY_CFG_DATA_MASK 0xf
#define PHY_CFG_ADDR_MASK 0x3f
-#define PHY_CFG_RD_MASK 0x3ff
#define PHY_CFG_WR_ENABLE 1
-#define PHY_CFG_WR_DISABLE 1
+#define PHY_CFG_WR_DISABLE 0
#define PHY_CFG_WR_SHIFT 0
#define PHY_CFG_WR_MASK 1
#define PHY_CFG_PLL_LOCK 0x10
--
2.49.0
next prev parent reply other threads:[~2025-06-30 22:25 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-30 22:24 [RESEND PATCH v9 0/4] PCI: rockchip: Improve driver quality Geraldo Nascimento
2025-06-30 22:24 ` [RESEND PATCH v9 1/4] PCI: rockchip: Use standard PCIe defines Geraldo Nascimento
2025-07-01 7:54 ` Philipp Stanner
2025-07-01 12:03 ` Geraldo Nascimento
2025-07-01 12:44 ` Manivannan Sadhasivam
2025-07-07 22:22 ` Bjorn Helgaas
2025-07-07 23:04 ` Geraldo Nascimento
2025-06-30 22:24 ` [RESEND PATCH v9 2/4] PCI: rockchip: Set Target Link Speed before retraining Geraldo Nascimento
2025-06-30 22:25 ` [RESEND PATCH v9 3/4] phy: rockchip-pcie: Enable all four lanes if required Geraldo Nascimento
2025-06-30 22:25 ` Geraldo Nascimento [this message]
2025-07-01 7:43 ` (subset) [RESEND PATCH v9 0/4] PCI: rockchip: Improve driver quality Manivannan Sadhasivam
2025-07-22 13:37 ` Vinod Koul
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