Re: [PATCH V12 01/12] PCI: Add #defines for some of PCIe spec r4.0 features

Vidya Sagar
2019-07-09T13:38:58Z

On 7/5/2019 7:16 PM, Vidya Sagar wrote:
Bjorn,
Apologies for pinging again about this.
Can you please provide Ack for this change so that Lorenzo can pick up this series?

Thanks,
Vidya Sagar

> On 7/1/2019 6:09 PM, Vidya Sagar wrote:
> Bjorn,
> Can you please provide Ack for this patch?
>
> Thanks,
> Vidya Sagar
>
>> Add #defines only for the Data Link Feature and Physical Layer 16.0 GT/s
>> features.
>>
>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>> Reviewed-by: Thierry Reding <treding@nvidia.com>
>> ---
>> Changes since [v11]:
>> * None
>>
>> Changes since [v10]:
>> * None
>>
>> Changes since [v9]:
>> * None
>>
>> Changes since [v8]:
>> * None
>>
>> Changes since [v7]:
>> * None
>>
>> Changes since [v6]:
>> * None
>>
>> Changes since [v5]:
>> * None
>>
>> Changes since [v4]:
>> * None
>>
>> Changes since [v3]:
>> * None
>>
>> Changes since [v2]:
>> * Updated commit message and description to explicitly mention that defines are
>>    added only for some of the features and not all.
>>
>> Changes since [v1]:
>> * None
>>
>>   include/uapi/linux/pci_regs.h | 22 +++++++++++++++++++++-
>>   1 file changed, 21 insertions(+), 1 deletion(-)
>>
>> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
>> index f28e562d7ca8..1c79f6a097d2 100644
>> --- a/include/uapi/linux/pci_regs.h
>> +++ b/include/uapi/linux/pci_regs.h
>> @@ -713,7 +713,9 @@
>>   #define PCI_EXT_CAP_ID_DPC    0x1D    /* Downstream Port Containment */
>>   #define PCI_EXT_CAP_ID_L1SS    0x1E    /* L1 PM Substates */
>>   #define PCI_EXT_CAP_ID_PTM    0x1F    /* Precision Time Measurement */
>> -#define PCI_EXT_CAP_ID_MAX    PCI_EXT_CAP_ID_PTM
>> +#define PCI_EXT_CAP_ID_DLF    0x25    /* Data Link Feature */
>> +#define PCI_EXT_CAP_ID_PL    0x26    /* Physical Layer 16.0 GT/s */
>> +#define PCI_EXT_CAP_ID_MAX    PCI_EXT_CAP_ID_PL
>>   #define PCI_EXT_CAP_DSN_SIZEOF    12
>>   #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40
>> @@ -1053,4 +1055,22 @@
>>   #define  PCI_L1SS_CTL1_LTR_L12_TH_SCALE    0xe0000000  /* LTR_L1.2_THRESHOLD_Scale */
>>   #define PCI_L1SS_CTL2        0x0c    /* Control 2 Register */
>> +/* Data Link Feature */
>> +#define PCI_DLF_CAP        0x04    /* Capabilities Register */
>> +#define  PCI_DLF_LOCAL_DLF_SUP_MASK    0x007fffff  /* Local Data Link Feature Supported */
>> +#define  PCI_DLF_EXCHANGE_ENABLE    0x80000000  /* Data Link Feature Exchange Enable */
>> +#define PCI_DLF_STS        0x08    /* Status Register */
>> +#define  PCI_DLF_REMOTE_DLF_SUP_MASK    0x007fffff  /* Remote Data Link Feature Supported */
>> +#define  PCI_DLF_REMOTE_DLF_SUP_VALID    0x80000000  /* Remote Data Link Feature Support Valid */
>> +
>> +/* Physical Layer 16.0 GT/s */
>> +#define PCI_PL_16GT_CAP        0x04    /* Capabilities Register */
>> +#define PCI_PL_16GT_CTRL    0x08    /* Control Register */
>> +#define PCI_PL_16GT_STS        0x0c    /* Status Register */
>> +#define PCI_PL_16GT_LDPM_STS    0x10    /* Local Data Parity Mismatch Status Register */
>> +#define PCI_PL_16GT_FRDPM_STS    0x14    /* First Retimer Data Parity Mismatch Status Register */
>> +#define PCI_PL_16GT_SRDPM_STS    0x18    /* Second Retimer Data Parity Mismatch Status Register */
>> +#define PCI_PL_16GT_RSVD    0x1C    /* Reserved */
>> +#define PCI_PL_16GT_LE_CTRL    0x20    /* Lane Equalization Control Register */
>> +
>>   #endif /* LINUX_PCI_REGS_H */
>>
>