From: "Jianjun Wang (王建军)" <Jianjun.Wang@mediatek.com>
To: "krzk@kernel.org" <krzk@kernel.org>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-mediatek@lists.infradead.org"
<linux-mediatek@lists.infradead.org>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"manivannan.sadhasivam@linaro.org"
<manivannan.sadhasivam@linaro.org>,
"conor+dt@kernel.org" <conor+dt@kernel.org>,
"robh@kernel.org" <robh@kernel.org>,
"kw@linux.com" <kw@linux.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
"Xavier Chang (張獻文)" <Xavier.Chang@mediatek.com>,
"lpieralisi@kernel.org" <lpieralisi@kernel.org>,
"Ryder Lee" <Ryder.Lee@mediatek.com>,
"AngeloGioacchino Del Regno"
<angelogioacchino.delregno@collabora.com>,
"krzk+dt@kernel.org" <krzk+dt@kernel.org>,
"matthias.bgg@gmail.com" <matthias.bgg@gmail.com>
Subject: Re: [PATCH 1/5] dt-bindings: PCI: mediatek-gen3: Add MT8196 support
Date: Wed, 8 Jan 2025 07:30:24 +0000 [thread overview]
Message-ID: <d7b26561b60f8aee2674dfebc45856d7fba305eb.camel@mediatek.com> (raw)
In-Reply-To: <14a456bd-3f24-4daf-9329-873d0f051a83@kernel.org>
On Wed, 2025-01-08 at 08:16 +0100, Krzysztof Kozlowski wrote:
> External email : Please do not click links or open attachments until
> you have verified the sender or the content.
>
>
> On 07/01/2025 09:43, Jianjun Wang (王建军) wrote:
> > On Mon, 2025-01-06 at 13:27 +0100, Krzysztof Kozlowski wrote:
> > > External email : Please do not click links or open attachments
> > > until
> > > you have verified the sender or the content.
> > >
> > >
> > > On 06/01/2025 10:26, Jianjun Wang (王建军) wrote:
> > > > On Fri, 2025-01-03 at 10:10 +0100, Krzysztof Kozlowski wrote:
> > > > > External email : Please do not click links or open
> > > > > attachments
> > > > > until
> > > > > you have verified the sender or the content.
> > > > >
> > > > >
> > > > > On Fri, Jan 03, 2025 at 02:00:11PM +0800, Jianjun Wang wrote:
> > > > > > + clock-names:
> > > > > > + items:
> > > > > > + - const: pl_250m
> > > > > > + - const: tl_26m
> > > > > > + - const: peri_26m
> > > > > > + - const: peri_mem
> > > > > > + - const: ahb_apb
> > > > > > + - const: low_power
> > > > > > +
> > > > > > + resets:
> > > > > > + minItems: 1
> > > > > > + maxItems: 2
> > > > > > +
> > > > > > + reset-names:
> > > > > > + minItems: 1
> > > > > > + maxItems: 2
> > > > >
> > > > > Why resets are flexible?
> > > >
> > > > There are two resets, one for MAC and another for PHY, some
> > > > platforms
> > > > may only use one of them.
> > >
> > > Even more questions. What does it mean use? Is it there or is it
> > > not?
> >
> > It will be used by calling the reset controller's APIs in the PCIe
> > controller driver. Ideally, it should be de-asserted before PCIe
> > initialization and should be asserted if PCIe powers down or the
> > driver
> > is removed.
>
> So it is there? Then drop minItems.
>
> >
> > > Platform like SoC? But this is one specific SoC, it cannot be
> > > used on
> > > different SoC.
> >
> > Yes, it should be SoC, each SoC have its own resets, and the number
> > of
> > resets for each SoC is defined by the hardware design, most SoCs
> > should
> > have one reset for MAC and one reset for PHY.
>
> You respond with some obvious things, so this review won't work.
> Properties are supposed to be constrained. Your arguments that
> something
> else has something else, do not apply. It does not matter what
> something
> else has.
>
> >
> > >
> > > >
> > > > Would you prefer to set the number of resets to a fixed value
> > > > for
> > > > specific platforms?
> > >
> > > Everything should be constrained to match hardware.
> >
> > For MT8196, there are 2 resets. Should I use a fixed item in this
> > case?
>
> Yes. I asked why this soc has this flexible and you speak about some
> other socs.
Got it, sorry for the noise, will fix it in the next version.
Thanks.
>
>
>
> Best regards,
> Krzysztof
>
next prev parent reply other threads:[~2025-01-08 7:30 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-01-03 6:00 [PATCH 0/5] PCI: mediatek-gen3: Add MT8196 support Jianjun Wang
2025-01-03 6:00 ` [PATCH 1/5] dt-bindings: " Jianjun Wang
2025-01-03 9:10 ` Krzysztof Kozlowski
2025-01-06 9:26 ` Jianjun Wang (王建军)
2025-01-06 12:27 ` Krzysztof Kozlowski
2025-01-07 8:43 ` Jianjun Wang (王建军)
2025-01-07 9:02 ` Chen-Yu Tsai
2025-01-08 6:53 ` Jianjun Wang (王建军)
2025-01-08 7:16 ` Krzysztof Kozlowski
2025-01-08 7:30 ` Jianjun Wang (王建军) [this message]
2025-01-03 9:26 ` AngeloGioacchino Del Regno
2025-01-06 9:19 ` Jianjun Wang (王建军)
2025-01-07 13:04 ` AngeloGioacchino Del Regno
2025-01-08 7:24 ` Jianjun Wang (王建军)
2025-01-03 6:00 ` [PATCH 2/5] " Jianjun Wang
2025-01-03 19:02 ` Bjorn Helgaas
2025-01-07 1:51 ` Jianjun Wang (王建军)
2025-01-03 6:00 ` [PATCH 3/5] PCI: mediatek-gen3: Disable ASPM L0s Jianjun Wang
2025-01-03 9:16 ` AngeloGioacchino Del Regno
2025-01-07 2:18 ` Jianjun Wang (王建军)
2025-01-07 11:44 ` AngeloGioacchino Del Regno
2025-01-07 23:07 ` Bjorn Helgaas
2025-01-03 19:15 ` Bjorn Helgaas
2025-01-07 2:44 ` Jianjun Wang (王建军)
2025-01-07 23:06 ` Bjorn Helgaas
2025-01-06 16:09 ` Manivannan Sadhasivam
2025-01-03 6:00 ` [PATCH 4/5] PCI: mediatek-gen3: Don't reply AXI slave error Jianjun Wang
2025-01-03 9:29 ` AngeloGioacchino Del Regno
2025-01-06 9:27 ` Jianjun Wang (王建军)
2025-01-03 19:19 ` Bjorn Helgaas
2025-01-06 9:31 ` Jianjun Wang (王建军)
2025-01-06 16:16 ` Manivannan Sadhasivam
2025-01-07 3:21 ` Jianjun Wang (王建军)
2025-01-03 6:00 ` [PATCH 5/5] PCI: mediatek-gen3: Keep PCIe power and clocks if suspend-to-idle Jianjun Wang
2025-01-03 9:14 ` AngeloGioacchino Del Regno
2025-01-03 19:13 ` Bjorn Helgaas
2025-01-06 16:23 ` Manivannan Sadhasivam
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