From: Sean Anderson <sean.anderson@linux.dev>
To: Bjorn Helgaas <helgaas@kernel.org>,
Stefan Roese <stefan.roese@mailbox.org>
Cc: linux-pci@vger.kernel.org,
Manivannan Sadhasivam <mani@kernel.org>,
Ravi Kumar Bandi <ravib@amazon.com>,
Thippeswamy Havalige <thippeswamy.havalige@amd.com>,
Michal Simek <michal.simek@amd.com>,
Bjorn Helgaas <bhelgaas@google.com>
Subject: Re: [PATCH v2] PCI: pcie-xilinx-dma-pl: Fix off-by-one INTx IRQ handling
Date: Tue, 21 Oct 2025 12:26:30 -0400 [thread overview]
Message-ID: <d8525e6e-7098-4bc3-abb1-4c0540b71c61@linux.dev> (raw)
In-Reply-To: <20251021155347.GA1191808@bhelgaas>
On 10/21/25 11:53, Bjorn Helgaas wrote:
> On Tue, Oct 21, 2025 at 05:43:22PM +0200, Stefan Roese wrote:
>> While testing with NVMe drives connected to the Versal QDMA PL PCIe RP
>> on our platform I noticed that with MSI disabled (e.g. via pci=nomsi)
>> the NVMe interrupts are not delivered to the host CPU resulting in
>> timeouts while probing.
>>
>> Debugging has shown, that the hwirq numbers passed to this device driver
>> (1...4, 1=INTA etc) need to get adjusted to match the numbers in the
>> controller registers bits (0...3).
>>
>> This patch now adds pci_irqd_intx_xlate to the INTx IRQ domain ops,
>> handling this IRQ number translation correctly.
>
> s/pcie-xilinx-dma-pl:/xilinx-xdma:/ # in subject
> s/has shown, that/has shown that/
> s/This patch now adds/Add/
> s/pci_irqd_intx_xlate/pci_irqd_intx_xlate()/
>
> We'll do this when applying, no need to repost for this.
>
> I wonder how many other drivers have this issue.
> pci_irqd_intx_xlate() is used only by:
>
> dwc/pci-dra7xx.c
> pcie-altera.c
> pcie-xilinx-nwl.c
> pcie-xilinx.c
> pcie-xilinx-dma-pl.c # this patch
>
> Is there something different about these drivers that means they need
> it when all the others don't?
I think many PCI controllers just don't differentiate between legacy
interrupts. e.g. I looked at NXP's LS1046 which is based on DWC and it
does
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
which I believe maps all root port legacy interrupts to a single shared
GIC interrupt. Which sort of defeats the purpose of swizzling, but most
stuff uses MSI(-X) now so I guess they figured a status register wasn't
worth the verification.
And yes, I don't think legacy interrupts are tested very much these
days.
--Sean
next prev parent reply other threads:[~2025-10-21 16:26 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-21 15:43 [PATCH v2] PCI: pcie-xilinx-dma-pl: Fix off-by-one INTx IRQ handling Stefan Roese
2025-10-21 15:53 ` Bjorn Helgaas
2025-10-21 16:02 ` Stefan Roese
2025-10-21 16:15 ` Bjorn Helgaas
2025-10-21 16:26 ` Sean Anderson [this message]
2025-10-21 17:30 ` Sean Anderson
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