From: Sathyanarayanan Kuppuswamy <sathyanarayanan.kuppuswamy@linux.intel.com>
To: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>,
linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-cxl@vger.kernel.org
Cc: Bjorn Helgaas <bhelgaas@google.com>,
oohall@gmail.com, Lukas Wunner <lukas@wunner.de>,
Mahesh J Salgaonkar <mahesh@linux.ibm.com>,
Alison Schofield <alison.schofield@intel.com>,
Vishal Verma <vishal.l.verma@intel.com>,
Ira Weiny <ira.weiny@intel.com>,
Ben Widawsky <bwidawsk@kernel.org>,
Dan Williams <dan.j.williams@intel.com>,
Jonathan Cameron <Jonathan.Cameron@Huawei.com>,
Yazen Ghannam <yazen.ghannam@amd.com>,
Terry Bowman <terry.bowman@amd.com>,
Robert Richter <rrichter@amd.com>
Subject: Re: [PATCH v2 3/3] cxl/pci: Replace host_bridge->native_aer with pcie_aer_is_native()
Date: Fri, 21 Jul 2023 17:17:05 -0700 [thread overview]
Message-ID: <d94a39e3-1822-1f3f-1118-6b2346f5e738@linux.intel.com> (raw)
In-Reply-To: <20230721214740.256602-4-Smita.KoralahalliChannabasappa@amd.com>
On 7/21/23 2:47 PM, Smita Koralahalli wrote:
> Reuse pcie_aer_is_native() to determine the native AER ownership.
Although it is straightforward, IMO, the commit log should include
few words about *why* you are making this change.
For example, usage of host_bride->native_aer does not cover command
line override of AER ownership. So use pcie_aer_is_native() to
determine the ownership.
With that fixed,
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
>
> Signed-off-by: Smita Koralahalli <Smita.KoralahalliChannabasappa@amd.com>
> ---
> v2:
> Replaced pcie_aer_is_native() at a later stage for automated
> backports.
> ---
> drivers/cxl/pci.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
> index 2323169b6e5f..44a21ab7add5 100644
> --- a/drivers/cxl/pci.c
> +++ b/drivers/cxl/pci.c
> @@ -529,7 +529,6 @@ static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type,
>
> static int cxl_pci_ras_unmask(struct pci_dev *pdev)
> {
> - struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus);
> struct cxl_dev_state *cxlds = pci_get_drvdata(pdev);
> void __iomem *addr;
> u32 orig_val, val, mask;
> @@ -542,7 +541,7 @@ static int cxl_pci_ras_unmask(struct pci_dev *pdev)
> }
>
> /* BIOS has PCIe AER error control */
> - if (!host_bridge->native_aer)
> + if (!pcie_aer_is_native(pdev))
> return 0;
>
> rc = pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap);
--
Sathyanarayanan Kuppuswamy
Linux Kernel Developer
next prev parent reply other threads:[~2023-07-22 0:17 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-21 21:47 [PATCH v2 0/3] PCI/AER, CXL: Fix appropriate _OSC check for CXL RAS Cap Smita Koralahalli
2023-07-21 21:47 ` [PATCH v2 1/3] cxl/pci: Fix appropriate checking for _OSC while handling CXL RAS registers Smita Koralahalli
2023-07-22 0:18 ` Sathyanarayanan Kuppuswamy
2023-07-24 21:59 ` Smita Koralahalli
2023-08-08 3:22 ` Dan Williams
2023-07-24 12:02 ` Robert Richter
2023-08-08 3:17 ` Dan Williams
2023-08-08 19:37 ` Smita Koralahalli
2023-07-21 21:47 ` [PATCH v2 2/3] PCI/AER: Export pcie_aer_is_native() Smita Koralahalli
2023-07-24 12:42 ` Robert Richter
2023-08-08 3:20 ` Dan Williams
2023-07-21 21:47 ` [PATCH v2 3/3] cxl/pci: Replace host_bridge->native_aer with pcie_aer_is_native() Smita Koralahalli
2023-07-22 0:17 ` Sathyanarayanan Kuppuswamy [this message]
2023-07-24 12:44 ` Robert Richter
2023-08-08 3:21 ` Dan Williams
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