From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09430C41513 for ; Sat, 22 Jul 2023 00:17:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230430AbjGVARI (ORCPT ); Fri, 21 Jul 2023 20:17:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40310 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229529AbjGVARH (ORCPT ); Fri, 21 Jul 2023 20:17:07 -0400 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E4FDB1705; Fri, 21 Jul 2023 17:17:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1689985027; x=1721521027; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=sVDYsKmJrI+FgtLdiHgy/Ei0RS4XwTYvF/jSUYneT+A=; b=B00VZbgLEZ8ng38GYURQGDno/fWt7Q/rikXkw0u8nDY+N9rMhBvP3FUk WSNzXi+CshSrnaeO6urfPeO1k3hVBnh1ZaBMGUlG50sEo/Xk4p/366E8Q 28UQYVWFjcdltXcxQVFd5Hz4GaGXJT7r7B+sCaRF3giwHD+KhXAI5aMhV k0PJqW/PB0INcZmJRYi7i5Ri+cCh7wLmnvfAVGtwOitq6Ldj2Zo8EyAyx taP/8rNkqC7/RYVeykdftRcCXR9Dx2V2NMuSBsd1+RVDkO4WL90fU3Ckj JzpBQS0objUvlSpXtXmcwXmsYgIrMDSSPkG9bwlyQQHO0+2XiKNfY9g7r Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10778"; a="369808751" X-IronPort-AV: E=Sophos;i="6.01,223,1684825200"; d="scan'208";a="369808751" Received: from orsmga007.jf.intel.com ([10.7.209.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2023 17:17:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10778"; a="719025040" X-IronPort-AV: E=Sophos;i="6.01,223,1684825200"; d="scan'208";a="719025040" Received: from cthomas-mobl1.amr.corp.intel.com (HELO [10.209.99.41]) ([10.209.99.41]) by orsmga007-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2023 17:17:06 -0700 Message-ID: Date: Fri, 21 Jul 2023 17:17:05 -0700 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Firefox/102.0 Thunderbird/102.13.0 Subject: Re: [PATCH v2 3/3] cxl/pci: Replace host_bridge->native_aer with pcie_aer_is_native() Content-Language: en-US To: Smita Koralahalli , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org Cc: Bjorn Helgaas , oohall@gmail.com, Lukas Wunner , Mahesh J Salgaonkar , Alison Schofield , Vishal Verma , Ira Weiny , Ben Widawsky , Dan Williams , Jonathan Cameron , Yazen Ghannam , Terry Bowman , Robert Richter References: <20230721214740.256602-1-Smita.KoralahalliChannabasappa@amd.com> <20230721214740.256602-4-Smita.KoralahalliChannabasappa@amd.com> From: Sathyanarayanan Kuppuswamy In-Reply-To: <20230721214740.256602-4-Smita.KoralahalliChannabasappa@amd.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On 7/21/23 2:47 PM, Smita Koralahalli wrote: > Reuse pcie_aer_is_native() to determine the native AER ownership. Although it is straightforward, IMO, the commit log should include few words about *why* you are making this change. For example, usage of host_bride->native_aer does not cover command line override of AER ownership. So use pcie_aer_is_native() to determine the ownership. With that fixed, Reviewed-by: Kuppuswamy Sathyanarayanan > > Signed-off-by: Smita Koralahalli > --- > v2: > Replaced pcie_aer_is_native() at a later stage for automated > backports. > --- > drivers/cxl/pci.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c > index 2323169b6e5f..44a21ab7add5 100644 > --- a/drivers/cxl/pci.c > +++ b/drivers/cxl/pci.c > @@ -529,7 +529,6 @@ static int cxl_pci_setup_regs(struct pci_dev *pdev, enum cxl_regloc_type type, > > static int cxl_pci_ras_unmask(struct pci_dev *pdev) > { > - struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus); > struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); > void __iomem *addr; > u32 orig_val, val, mask; > @@ -542,7 +541,7 @@ static int cxl_pci_ras_unmask(struct pci_dev *pdev) > } > > /* BIOS has PCIe AER error control */ > - if (!host_bridge->native_aer) > + if (!pcie_aer_is_native(pdev)) > return 0; > > rc = pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap); -- Sathyanarayanan Kuppuswamy Linux Kernel Developer