From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Return-Path: Subject: Re: [PATCH V7 0/5] PCI/ASPM: reconfigure ASPM following hotplug for POLICY_DEFAULT To: Rajat Jain References: <1490880636-30542-1-git-send-email-okaya@codeaurora.org> <7c48ca8b-b834-3257-91dc-77e9d19def6c@codeaurora.org> <92EBB4272BF81E4089A7126EC1E7B28466761383@IRSMSX101.ger.corp.intel.com> <92EBB4272BF81E4089A7126EC1E7B2846676271D@IRSMSX101.ger.corp.intel.com> <951505b8-9580-7131-2f14-de92817190a7@codeaurora.org> From: Sinan Kaya Message-ID: Date: Thu, 6 Apr 2017 20:34:13 -0400 MIME-Version: 1.0 In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Patel, Mayurkumar" , "linux-pci@vger.kernel.org" , "timur@codeaurora.org" , "linux-arm-msm@vger.kernel.org" , Bjorn Helgaas , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+bjorn=helgaas.com@lists.infradead.org List-ID: Hi Rajat, On 4/6/2017 1:10 PM, Rajat Jain wrote: > Thanks, The above commit specifically adds a comment to > pcie_aspm_check_latency(), because I wanted to leave a note > highlighting that potentially, we could add a more stringent check for > exit latency for L1SS. But that has nothing to do with how we are > configuring or enabling / disabling the L1 substates. I saw your name in two L1SS reviews. I wanted to pull you into the discussion as an L1SS expert. I didn't want to imply that there was something wrong with the review. Apologies for that. Sinan -- Sinan Kaya Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc. Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel