[PATCH v3 0/9] add new irq api to pcie-designware

[PATCH v3 0/9] add new irq api to pcie-designware

[Gustavo Pimentel]

This patch series adds the new interrupt api to pcie-designware make it
possible to use features like MSIX.
The work consisted of adapting the pcie-designware-host and each SoC
specific driver.
The patch set was made against the Bjorn' next branch.
A new patch set (v3) was created that includes Kishon's fixes (pci end
point error and a dra7xx warning) in file
0007-pci-keystone-SoC-driver-adapted-to-new-irq-API.patch.

Gustavo Pimentel (9):
  pci: adding new irq api to pci-designware
  pci: exynos SoC driver adapted to new irq API
  pci: imx6 SoC driver adapted to new irq API
  pci: artpec6 SoC driver adapted to new irq API
  pci: generic PCIe DW driver adapted to new irq API
  pci: qcom SoC driver adapted to new irq API
  pci: keystone SoC driver adapted to new irq API
  pci: removing old irq api from pcie-designware
  pci: remove limitation of the number of the available IRQs

 drivers/pci/dwc/pci-exynos.c           |  18 --
 drivers/pci/dwc/pci-imx6.c             |  18 --
 drivers/pci/dwc/pci-keystone-dw.c      |  88 +-------
 drivers/pci/dwc/pci-keystone.c         |   1 +
 drivers/pci/dwc/pci-keystone.h         |   4 +-
 drivers/pci/dwc/pci-layerscape.c       |   4 +-
 drivers/pci/dwc/pcie-artpec6.c         |  18 --
 drivers/pci/dwc/pcie-designware-host.c | 391 +++++++++++++++++++--------------
 drivers/pci/dwc/pcie-designware-plat.c |  16 --
 drivers/pci/dwc/pcie-designware.h      |  30 ++-
 drivers/pci/dwc/pcie-qcom.c            |  16 --
 11 files changed, 254 insertions(+), 350 deletions(-)

-- 
2.7.4

[PATCH v3 1/9] pci: adding new irq api to pci-designware

[Gustavo Pimentel]

This patch adds the new interrupt api to pcie-designware, keeping the old
one. Although the old API is still available, pcie-designware initiates
with the new one.

Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
---
Change v1->v2:
- num_vectors is now not configurable by DT. Now it is 32 by default and
can be overridden by any specific SoC driver.
Change v2->v3:
- Nothing changed, just to follow the patch set version.

 drivers/pci/dwc/pcie-designware-host.c | 282 +++++++++++++++++++++++++++++----
 drivers/pci/dwc/pcie-designware.h      |  17 ++
 2 files changed, 272 insertions(+), 27 deletions(-)

diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
index 81e2157..289d476 100644
--- a/drivers/pci/dwc/pcie-designware-host.c
+++ b/drivers/pci/dwc/pcie-designware-host.c
@@ -11,6 +11,7 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/irqchip/chained_irq.h>
 #include <linux/irqdomain.h>
 #include <linux/of_address.h>
 #include <linux/of_pci.h>
@@ -53,6 +54,30 @@ static struct irq_chip dw_msi_irq_chip = {
 	.irq_unmask = pci_msi_unmask_irq,
 };
 
+static void dw_msi_mask_irq(struct irq_data *d)
+{
+	pci_msi_mask_irq(d);
+	irq_chip_mask_parent(d);
+}
+
+static void dw_msi_unmask_irq(struct irq_data *d)
+{
+	pci_msi_unmask_irq(d);
+	irq_chip_unmask_parent(d);
+}
+
+static struct irq_chip dw_pcie_msi_irq_chip = {
+	.name = "PCI-MSI",
+	.irq_mask = dw_msi_mask_irq,
+	.irq_unmask = dw_msi_unmask_irq,
+};
+
+static struct msi_domain_info dw_pcie_msi_domain_info = {
+	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
+		     MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
+	.chip	= &dw_pcie_msi_irq_chip,
+};
+
 /* MSI int handler */
 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
 {
@@ -81,6 +106,191 @@ irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
 	return ret;
 }
 
+/* Chained MSI interrupt service routine */
+static void dw_chained_msi_isr(struct irq_desc *desc)
+{
+	struct irq_chip *chip = irq_desc_get_chip(desc);
+	struct pcie_port *pp;
+	struct dw_pcie *pci;
+
+	chained_irq_enter(chip, desc);
+	pci = irq_desc_get_handler_data(desc);
+	pp = &pci->pp;
+
+	dw_handle_msi_irq(pp);
+
+	chained_irq_exit(chip, desc);
+}
+
+static void dw_pci_setup_msi_msg(struct irq_data *data, struct msi_msg *msg)
+{
+	struct dw_pcie *pci = irq_data_get_irq_chip_data(data);
+	struct pcie_port *pp = &pci->pp;
+	u64 msi_target;
+
+	if (pp->ops->get_msi_addr)
+		msi_target = pp->ops->get_msi_addr(pp);
+	else
+		msi_target = virt_to_phys((void *)pp->msi_data);
+
+	msg->address_lo = lower_32_bits(msi_target);
+	msg->address_hi = upper_32_bits(msi_target);
+
+	if (pp->ops->get_msi_data)
+		msg->data = pp->ops->get_msi_data(pp, data->hwirq);
+	else
+		msg->data = data->hwirq;
+
+	dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n",
+		(int)data->hwirq, msg->address_hi, msg->address_lo);
+}
+
+static int dw_pci_msi_set_affinity(struct irq_data *irq_data,
+				   const struct cpumask *mask, bool force)
+{
+	return -EINVAL;
+}
+
+static void dw_pci_bottom_mask(struct irq_data *data)
+{
+	struct dw_pcie *pci = irq_data_get_irq_chip_data(data);
+	struct pcie_port *pp = &pci->pp;
+	unsigned int res, bit, ctrl;
+	unsigned long flags;
+
+	spin_lock_irqsave(&pp->lock, flags);
+
+	if (pp->ops->msi_clear_irq)
+		pp->ops->msi_clear_irq(pp, data->hwirq);
+	else {
+		ctrl = data->hwirq / 32;
+		res = ctrl * 12;
+		bit = data->hwirq % 32;
+
+		pp->irq_status[ctrl] &= ~(1 << bit);
+		dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4,
+				    pp->irq_status[ctrl]);
+	}
+
+	spin_unlock_irqrestore(&pp->lock, flags);
+}
+
+static void dw_pci_bottom_unmask(struct irq_data *data)
+{
+	struct dw_pcie *pci = irq_data_get_irq_chip_data(data);
+	struct pcie_port *pp = &pci->pp;
+	unsigned int res, bit, ctrl;
+	unsigned long flags;
+
+	spin_lock_irqsave(&pp->lock, flags);
+
+	if (pp->ops->msi_set_irq)
+		pp->ops->msi_set_irq(pp, data->hwirq);
+	else {
+		ctrl = data->hwirq / 32;
+		res = ctrl * 12;
+		bit = data->hwirq % 32;
+
+		pp->irq_status[ctrl] |= 1 << bit;
+		dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4,
+				    pp->irq_status[ctrl]);
+	}
+
+	spin_unlock_irqrestore(&pp->lock, flags);
+}
+
+static struct irq_chip dw_pci_msi_bottom_irq_chip = {
+	.name = "DWPCI-MSI",
+	.irq_compose_msi_msg = dw_pci_setup_msi_msg,
+	.irq_set_affinity = dw_pci_msi_set_affinity,
+	.irq_mask = dw_pci_bottom_mask,
+	.irq_unmask = dw_pci_bottom_unmask,
+};
+
+static int dw_pcie_irq_domain_alloc(struct irq_domain *domain,
+				    unsigned int virq, unsigned int nr_irqs,
+				    void *args)
+{
+	struct dw_pcie *pci = domain->host_data;
+	struct pcie_port *pp = &pci->pp;
+	unsigned long flags;
+	unsigned long bit;
+	u32 i;
+
+	spin_lock_irqsave(&pp->lock, flags);
+
+	bit = bitmap_find_next_zero_area(pp->msi_irq_in_use, pp->num_vectors, 0,
+					 nr_irqs, 0);
+
+	if (bit >= pp->num_vectors) {
+		spin_unlock_irqrestore(&pp->lock, flags);
+		return -ENOSPC;
+	}
+
+	bitmap_set(pp->msi_irq_in_use, bit, nr_irqs);
+
+	spin_unlock_irqrestore(&pp->lock, flags);
+
+	for (i = 0; i < nr_irqs; i++)
+		irq_domain_set_info(domain, virq + i, bit + i,
+				    &dw_pci_msi_bottom_irq_chip,
+				    domain->host_data, handle_simple_irq,
+				    NULL, NULL);
+
+	return 0;
+}
+
+static void dw_pcie_irq_domain_free(struct irq_domain *domain,
+				    unsigned int virq, unsigned int nr_irqs)
+{
+	struct irq_data *data = irq_domain_get_irq_data(domain, virq);
+	struct dw_pcie *pci = irq_data_get_irq_chip_data(data);
+	struct pcie_port *pp = &pci->pp;
+	unsigned long flags;
+
+	spin_lock_irqsave(&pp->lock, flags);
+	bitmap_clear(pp->msi_irq_in_use, data->hwirq, nr_irqs);
+	spin_unlock_irqrestore(&pp->lock, flags);
+}
+
+static const struct irq_domain_ops dw_pcie_msi_domain_ops = {
+	.alloc	= dw_pcie_irq_domain_alloc,
+	.free	= dw_pcie_irq_domain_free,
+};
+
+int dw_pcie_allocate_domains(struct dw_pcie *pci)
+{
+	struct pcie_port *pp = &pci->pp;
+	struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node);
+
+	pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors,
+					       &dw_pcie_msi_domain_ops, pci);
+	if (!pp->irq_domain) {
+		dev_err(pci->dev, "failed to create IRQ domain\n");
+		return -ENOMEM;
+	}
+
+	pp->msi_domain = pci_msi_create_irq_domain(fwnode,
+						   &dw_pcie_msi_domain_info,
+						   pp->irq_domain);
+	if (!pp->msi_domain) {
+		dev_err(pci->dev, "failed to create MSI domain\n");
+		irq_domain_remove(pp->irq_domain);
+		return -ENOMEM;
+	}
+
+	return 0;
+}
+
+void dw_pcie_free_msi(struct pcie_port *pp)
+{
+	irq_set_chained_handler(pp->msi_irq, NULL);
+	irq_set_handler_data(pp->msi_irq, NULL);
+
+	irq_domain_remove(pp->msi_domain);
+	irq_domain_remove(pp->irq_domain);
+}
+
 void dw_pcie_msi_init(struct pcie_port *pp)
 {
 	u64 msi_target;
@@ -90,20 +300,21 @@ void dw_pcie_msi_init(struct pcie_port *pp)
 
 	/* program the msi_data */
 	dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
-			    (u32)(msi_target & 0xffffffff));
+			    lower_32_bits(msi_target));
 	dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4,
-			    (u32)(msi_target >> 32 & 0xffffffff));
+			    upper_32_bits(msi_target));
 }
 
 static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
 {
-	unsigned int res, bit, val;
+	unsigned int res, bit, ctrl;
 
-	res = (irq / 32) * 12;
+	ctrl = irq / 32;
+	res = ctrl * 12;
 	bit = irq % 32;
-	dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
-	val &= ~(1 << bit);
-	dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
+	pp->irq_status[ctrl] &= ~(1 << bit);
+	dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4,
+			    pp->irq_status[ctrl]);
 }
 
 static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
@@ -125,13 +336,14 @@ static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
 
 static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
 {
-	unsigned int res, bit, val;
+	unsigned int res, bit, ctrl;
 
-	res = (irq / 32) * 12;
+	ctrl = irq / 32;
+	res = ctrl * 12;
 	bit = irq % 32;
-	dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
-	val |= 1 << bit;
-	dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
+	pp->irq_status[ctrl] |= 1 << bit;
+	dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4,
+			    pp->irq_status[ctrl]);
 }
 
 static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
@@ -279,11 +491,13 @@ int dw_pcie_host_init(struct pcie_port *pp)
 	struct device *dev = pci->dev;
 	struct device_node *np = dev->of_node;
 	struct platform_device *pdev = to_platform_device(dev);
+	struct resource_entry *win, *tmp;
 	struct pci_bus *bus, *child;
 	struct pci_host_bridge *bridge;
 	struct resource *cfg_res;
 	int i, ret;
-	struct resource_entry *win, *tmp;
+
+	spin_lock_init(&pci->pp.lock);
 
 	cfg_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config");
 	if (cfg_res) {
@@ -382,18 +596,32 @@ int dw_pcie_host_init(struct pcie_port *pp)
 		pci->num_viewport = 2;
 
 	if (IS_ENABLED(CONFIG_PCI_MSI)) {
-		if (!pp->ops->msi_host_init) {
-			pp->irq_domain = irq_domain_add_linear(dev->of_node,
-						MAX_MSI_IRQS, &msi_domain_ops,
-						&dw_pcie_msi_chip);
-			if (!pp->irq_domain) {
-				dev_err(dev, "irq domain init failed\n");
-				ret = -ENXIO;
+		/*
+		 * If a specific SoC driver needs to change the
+		 * default number of vectors, it needs to implement
+		 * the set_num_vectors callback.
+		 */
+		if (!pp->ops->set_num_vectors) {
+			pp->num_vectors = MSI_DEF_NUM_VECTORS;
+		} else {
+			pp->ops->set_num_vectors(pp);
+
+			if (pp->num_vectors > MAX_MSI_IRQS ||
+			    pp->num_vectors == 0) {
+				dev_err(dev,
+					"Invalid number of vectors\n");
 				goto error;
 			}
+		}
 
-			for (i = 0; i < MAX_MSI_IRQS; i++)
-				irq_create_mapping(pp->irq_domain, i);
+		if (!pp->ops->msi_host_init) {
+			ret = dw_pcie_allocate_domains(pci);
+			if (ret)
+				goto error;
+
+			irq_set_chained_handler_and_data(pci->pp.msi_irq,
+							 dw_chained_msi_isr,
+							 pci);
 		} else {
 			ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip);
 			if (ret < 0)
@@ -415,10 +643,6 @@ int dw_pcie_host_init(struct pcie_port *pp)
 	bridge->ops = &dw_pcie_ops;
 	bridge->map_irq = of_irq_parse_and_map_pci;
 	bridge->swizzle_irq = pci_common_swizzle;
-	if (IS_ENABLED(CONFIG_PCI_MSI)) {
-		bridge->msi = &dw_pcie_msi_chip;
-		dw_pcie_msi_chip.dev = dev;
-	}
 
 	ret = pci_scan_root_bus_bridge(bridge);
 	if (ret)
@@ -587,11 +811,15 @@ static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
 
 void dw_pcie_setup_rc(struct pcie_port *pp)
 {
-	u32 val;
+	u32 val, ctrl;
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 
 	dw_pcie_setup(pci);
 
+	/* Initialize IRQ Status array */
+	for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++)
+		dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + (ctrl * 12), 4,
+				    &pp->irq_status[ctrl]);
 	/* setup RC BARs */
 	dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0x00000004);
 	dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x00000000);
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index e5d9d77..6178251 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -112,6 +112,7 @@
  */
 #define MAX_MSI_IRQS			32
 #define MAX_MSI_CTRLS			(MAX_MSI_IRQS / 32)
+#define MSI_DEF_NUM_VECTORS		32
 
 struct pcie_port;
 struct dw_pcie;
@@ -143,6 +144,7 @@ struct dw_pcie_host_ops {
 	phys_addr_t (*get_msi_addr)(struct pcie_port *pp);
 	u32 (*get_msi_data)(struct pcie_port *pp, int pos);
 	void (*scan_bus)(struct pcie_port *pp);
+	void (*set_num_vectors)(struct pcie_port *pp);
 	int (*msi_host_init)(struct pcie_port *pp, struct msi_controller *chip);
 };
 
@@ -168,7 +170,11 @@ struct pcie_port {
 	const struct dw_pcie_host_ops *ops;
 	int			msi_irq;
 	struct irq_domain	*irq_domain;
+	struct irq_domain	*msi_domain;
 	unsigned long		msi_data;
+	u32			num_vectors;
+	u32			irq_status[MAX_MSI_CTRLS];
+	spinlock_t		lock;
 	DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
 };
 
@@ -308,8 +314,10 @@ static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci)
 #ifdef CONFIG_PCIE_DW_HOST
 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp);
 void dw_pcie_msi_init(struct pcie_port *pp);
+void dw_pcie_free_msi(struct pcie_port *pp);
 void dw_pcie_setup_rc(struct pcie_port *pp);
 int dw_pcie_host_init(struct pcie_port *pp);
+int dw_pcie_allocate_domains(struct dw_pcie *pci);
 #else
 static inline irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
 {
@@ -320,6 +328,10 @@ static inline void dw_pcie_msi_init(struct pcie_port *pp)
 {
 }
 
+static inline void dw_pcie_free_msi(struct pcie_port *pp)
+{
+}
+
 static inline void dw_pcie_setup_rc(struct pcie_port *pp)
 {
 }
@@ -328,6 +340,11 @@ static inline int dw_pcie_host_init(struct pcie_port *pp)
 {
 	return 0;
 }
+
+static inline int dw_pcie_allocate_domains(struct dw_pcie *pci)
+{
+	return 0;
+}
 #endif
 
 #ifdef CONFIG_PCIE_DW_EP
-- 
2.7.4

[PATCH v3 2/9] pci: exynos SoC driver adapted to new irq API

[Gustavo Pimentel]

This patch adapts Exynos SoC specific driver to use the new interrupt api
available in pcie-designware.

Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
Change v2->v3:
- Nothing changed, just to follow the patch set version.

 drivers/pci/dwc/pci-exynos.c | 18 ------------------
 1 file changed, 18 deletions(-)

diff --git a/drivers/pci/dwc/pci-exynos.c b/drivers/pci/dwc/pci-exynos.c
index 5596fde..d044952 100644
--- a/drivers/pci/dwc/pci-exynos.c
+++ b/drivers/pci/dwc/pci-exynos.c
@@ -490,15 +490,6 @@ static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg)
 	return IRQ_HANDLED;
 }
 
-static irqreturn_t exynos_pcie_msi_irq_handler(int irq, void *arg)
-{
-	struct exynos_pcie *ep = arg;
-	struct dw_pcie *pci = ep->pci;
-	struct pcie_port *pp = &pci->pp;
-
-	return dw_handle_msi_irq(pp);
-}
-
 static void exynos_pcie_msi_init(struct exynos_pcie *ep)
 {
 	struct dw_pcie *pci = ep->pci;
@@ -624,15 +615,6 @@ static int __init exynos_add_pcie_port(struct exynos_pcie *ep,
 			dev_err(dev, "failed to get msi irq\n");
 			return pp->msi_irq;
 		}
-
-		ret = devm_request_irq(dev, pp->msi_irq,
-					exynos_pcie_msi_irq_handler,
-					IRQF_SHARED | IRQF_NO_THREAD,
-					"exynos-pcie", ep);
-		if (ret) {
-			dev_err(dev, "failed to request msi irq\n");
-			return ret;
-		}
 	}
 
 	pp->root_bus_nr = -1;
-- 
2.7.4

[PATCH v3 3/9] pci: imx6 SoC driver adapted to new irq API

[Gustavo Pimentel]

This patch adapts imx6 SoC specific driver to use the new interrupt api
available in pcie-designware.

Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
Change v2->v3:
- Nothing changed, just to follow the patch set version.

 drivers/pci/dwc/pci-imx6.c | 18 ------------------
 1 file changed, 18 deletions(-)

diff --git a/drivers/pci/dwc/pci-imx6.c b/drivers/pci/dwc/pci-imx6.c
index b734835..d2314cb 100644
--- a/drivers/pci/dwc/pci-imx6.c
+++ b/drivers/pci/dwc/pci-imx6.c
@@ -545,15 +545,6 @@ static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
 	return -EINVAL;
 }
 
-static irqreturn_t imx6_pcie_msi_handler(int irq, void *arg)
-{
-	struct imx6_pcie *imx6_pcie = arg;
-	struct dw_pcie *pci = imx6_pcie->pci;
-	struct pcie_port *pp = &pci->pp;
-
-	return dw_handle_msi_irq(pp);
-}
-
 static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
 {
 	struct dw_pcie *pci = imx6_pcie->pci;
@@ -677,15 +668,6 @@ static int imx6_add_pcie_port(struct imx6_pcie *imx6_pcie,
 			dev_err(dev, "failed to get MSI irq\n");
 			return -ENODEV;
 		}
-
-		ret = devm_request_irq(dev, pp->msi_irq,
-				       imx6_pcie_msi_handler,
-				       IRQF_SHARED | IRQF_NO_THREAD,
-				       "mx6-pcie-msi", imx6_pcie);
-		if (ret) {
-			dev_err(dev, "failed to request MSI irq\n");
-			return ret;
-		}
 	}
 
 	pp->root_bus_nr = -1;
-- 
2.7.4

[PATCH v3 4/9] pci: artpec6 SoC driver adapted to new irq API

[Gustavo Pimentel]

This patch adapts artpec6 SoC specific driver to use the new interrupt api
available in pcie-designware.

Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
Change v2->v3:
- Nothing changed, just to follow the patch set version.

 drivers/pci/dwc/pcie-artpec6.c | 18 ------------------
 1 file changed, 18 deletions(-)

diff --git a/drivers/pci/dwc/pcie-artpec6.c b/drivers/pci/dwc/pcie-artpec6.c
index 6653619..d169c33 100644
--- a/drivers/pci/dwc/pcie-artpec6.c
+++ b/drivers/pci/dwc/pcie-artpec6.c
@@ -184,15 +184,6 @@ static const struct dw_pcie_host_ops artpec6_pcie_host_ops = {
 	.host_init = artpec6_pcie_host_init,
 };
 
-static irqreturn_t artpec6_pcie_msi_handler(int irq, void *arg)
-{
-	struct artpec6_pcie *artpec6_pcie = arg;
-	struct dw_pcie *pci = artpec6_pcie->pci;
-	struct pcie_port *pp = &pci->pp;
-
-	return dw_handle_msi_irq(pp);
-}
-
 static int artpec6_add_pcie_port(struct artpec6_pcie *artpec6_pcie,
 				 struct platform_device *pdev)
 {
@@ -207,15 +198,6 @@ static int artpec6_add_pcie_port(struct artpec6_pcie *artpec6_pcie,
 			dev_err(dev, "failed to get MSI irq\n");
 			return pp->msi_irq;
 		}
-
-		ret = devm_request_irq(dev, pp->msi_irq,
-				       artpec6_pcie_msi_handler,
-				       IRQF_SHARED | IRQF_NO_THREAD,
-				       "artpec6-pcie-msi", artpec6_pcie);
-		if (ret) {
-			dev_err(dev, "failed to request MSI irq\n");
-			return ret;
-		}
 	}
 
 	pp->root_bus_nr = -1;
-- 
2.7.4

[PATCH v3 5/9] pci: generic PCIe DW driver adapted to new irq API

[Gustavo Pimentel]

This patch adapts the generic PCIe DW driver to use the new interrupt api
available in pcie-designware.

Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
Change v2->v3:
- Nothing changed, just to follow the patch set version.

 drivers/pci/dwc/pcie-designware-plat.c | 16 ----------------
 1 file changed, 16 deletions(-)

diff --git a/drivers/pci/dwc/pcie-designware-plat.c b/drivers/pci/dwc/pcie-designware-plat.c
index 168e238..c148152 100644
--- a/drivers/pci/dwc/pcie-designware-plat.c
+++ b/drivers/pci/dwc/pcie-designware-plat.c
@@ -28,13 +28,6 @@ struct dw_plat_pcie {
 	struct dw_pcie		*pci;
 };
 
-static irqreturn_t dw_plat_pcie_msi_irq_handler(int irq, void *arg)
-{
-	struct pcie_port *pp = arg;
-
-	return dw_handle_msi_irq(pp);
-}
-
 static int dw_plat_pcie_host_init(struct pcie_port *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
@@ -66,15 +59,6 @@ static int dw_plat_add_pcie_port(struct pcie_port *pp,
 		pp->msi_irq = platform_get_irq(pdev, 0);
 		if (pp->msi_irq < 0)
 			return pp->msi_irq;
-
-		ret = devm_request_irq(dev, pp->msi_irq,
-					dw_plat_pcie_msi_irq_handler,
-					IRQF_SHARED | IRQF_NO_THREAD,
-					"dw-plat-pcie-msi", pp);
-		if (ret) {
-			dev_err(dev, "failed to request MSI IRQ\n");
-			return ret;
-		}
 	}
 
 	pp->root_bus_nr = -1;
-- 
2.7.4

[PATCH v3 6/9] pci: qcom SoC driver adapted to new irq API

[Gustavo Pimentel]

This patch adapts Qcom SoC specific driver to use the new interrupt api
available in pcie-designware.

Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
Change v2->v3:
- Nothing changed, just to follow the patch set version.

 drivers/pci/dwc/pcie-qcom.c | 16 ----------------
 1 file changed, 16 deletions(-)

diff --git a/drivers/pci/dwc/pcie-qcom.c b/drivers/pci/dwc/pcie-qcom.c
index ce7ba5b..3cc1a42 100644
--- a/drivers/pci/dwc/pcie-qcom.c
+++ b/drivers/pci/dwc/pcie-qcom.c
@@ -188,13 +188,6 @@ static void qcom_ep_reset_deassert(struct qcom_pcie *pcie)
 	usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500);
 }
 
-static irqreturn_t qcom_pcie_msi_irq_handler(int irq, void *arg)
-{
-	struct pcie_port *pp = arg;
-
-	return dw_handle_msi_irq(pp);
-}
-
 static int qcom_pcie_establish_link(struct qcom_pcie *pcie)
 {
 	struct dw_pcie *pci = pcie->pci;
@@ -1270,15 +1263,6 @@ static int qcom_pcie_probe(struct platform_device *pdev)
 		pp->msi_irq = platform_get_irq_byname(pdev, "msi");
 		if (pp->msi_irq < 0)
 			return pp->msi_irq;
-
-		ret = devm_request_irq(dev, pp->msi_irq,
-				       qcom_pcie_msi_irq_handler,
-				       IRQF_SHARED | IRQF_NO_THREAD,
-				       "qcom-pcie-msi", pp);
-		if (ret) {
-			dev_err(dev, "cannot request msi irq\n");
-			return ret;
-		}
 	}
 
 	ret = phy_init(pcie->phy);
-- 
2.7.4

[PATCH v3 7/9] pci: keystone SoC driver adapted to new irq API

[Gustavo Pimentel]

This patch adapts Keystone SoC specific driver to use the new interrupt api
available in pcie-designware. A new callback was added to dw_pcie_host_ops
to handle a specific Keystone function and msi_host_init callback is
changed to simplify the access to pci data structure for keystone all SoC
drivers that use the structure.

Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
---
Change v1->v2:
- Removed hardcoded num_vectors configuration (now it is done in the core driver by default)
Change v2->v3:
- 





 drivers/pci/dwc/pci-keystone-dw.c      | 88 ++--------------------------------
 drivers/pci/dwc/pci-keystone.c         |  1 +
 drivers/pci/dwc/pci-keystone.h         |  4 +-
 drivers/pci/dwc/pci-layerscape.c       |  3 +-
 drivers/pci/dwc/pcie-designware-host.c | 19 ++++++--
 drivers/pci/dwc/pcie-designware.h      |  3 +-
 6 files changed, 26 insertions(+), 92 deletions(-)

diff --git a/drivers/pci/dwc/pci-keystone-dw.c b/drivers/pci/dwc/pci-keystone-dw.c
index 2fb20b8..4fe4ab3 100644
--- a/drivers/pci/dwc/pci-keystone-dw.c
+++ b/drivers/pci/dwc/pci-keystone-dw.c
@@ -124,19 +124,15 @@ void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset)
 	}
 }
 
-static void ks_dw_pcie_msi_irq_ack(struct irq_data *d)
+void ks_dw_pcie_msi_irq_ack(int irq, struct pcie_port *pp)
 {
 	u32 offset, reg_offset, bit_pos;
 	struct keystone_pcie *ks_pcie;
-	struct msi_desc *msi;
-	struct pcie_port *pp;
 	struct dw_pcie *pci;
 
-	msi = irq_data_get_msi_desc(d);
-	pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
 	pci = to_dw_pcie_from_pp(pp);
 	ks_pcie = to_keystone_pcie(pci);
-	offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
+	offset = irq - irq_linear_revmap(pp->irq_domain, 0);
 	update_reg_offset_bit_pos(offset, &reg_offset, &bit_pos);
 
 	ks_dw_app_writel(ks_pcie, MSI0_IRQ_STATUS + (reg_offset << 4),
@@ -166,85 +162,9 @@ void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
 			 BIT(bit_pos));
 }
 
-static void ks_dw_pcie_msi_irq_mask(struct irq_data *d)
+int ks_dw_pcie_msi_host_init(struct dw_pcie *pci, struct msi_controller *chip)
 {
-	struct msi_desc *msi;
-	struct pcie_port *pp;
-	u32 offset;
-
-	msi = irq_data_get_msi_desc(d);
-	pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
-	offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
-
-	/* Mask the end point if PVM implemented */
-	if (IS_ENABLED(CONFIG_PCI_MSI)) {
-		if (msi->msi_attrib.maskbit)
-			pci_msi_mask_irq(d);
-	}
-
-	ks_dw_pcie_msi_clear_irq(pp, offset);
-}
-
-static void ks_dw_pcie_msi_irq_unmask(struct irq_data *d)
-{
-	struct msi_desc *msi;
-	struct pcie_port *pp;
-	u32 offset;
-
-	msi = irq_data_get_msi_desc(d);
-	pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
-	offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
-
-	/* Mask the end point if PVM implemented */
-	if (IS_ENABLED(CONFIG_PCI_MSI)) {
-		if (msi->msi_attrib.maskbit)
-			pci_msi_unmask_irq(d);
-	}
-
-	ks_dw_pcie_msi_set_irq(pp, offset);
-}
-
-static struct irq_chip ks_dw_pcie_msi_irq_chip = {
-	.name = "Keystone-PCIe-MSI-IRQ",
-	.irq_ack = ks_dw_pcie_msi_irq_ack,
-	.irq_mask = ks_dw_pcie_msi_irq_mask,
-	.irq_unmask = ks_dw_pcie_msi_irq_unmask,
-};
-
-static int ks_dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
-			      irq_hw_number_t hwirq)
-{
-	irq_set_chip_and_handler(irq, &ks_dw_pcie_msi_irq_chip,
-				 handle_level_irq);
-	irq_set_chip_data(irq, domain->host_data);
-
-	return 0;
-}
-
-static const struct irq_domain_ops ks_dw_pcie_msi_domain_ops = {
-	.map = ks_dw_pcie_msi_map,
-};
-
-int ks_dw_pcie_msi_host_init(struct pcie_port *pp, struct msi_controller *chip)
-{
-	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
-	struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
-	struct device *dev = pci->dev;
-	int i;
-
-	pp->irq_domain = irq_domain_add_linear(ks_pcie->msi_intc_np,
-					MAX_MSI_IRQS,
-					&ks_dw_pcie_msi_domain_ops,
-					chip);
-	if (!pp->irq_domain) {
-		dev_err(dev, "irq domain init failed\n");
-		return -ENXIO;
-	}
-
-	for (i = 0; i < MAX_MSI_IRQS; i++)
-		irq_create_mapping(pp->irq_domain, i);
-
-	return 0;
+	return dw_pcie_allocate_domains(pci);
 }
 
 void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie)
diff --git a/drivers/pci/dwc/pci-keystone.c b/drivers/pci/dwc/pci-keystone.c
index 5bee3af..76901fa 100644
--- a/drivers/pci/dwc/pci-keystone.c
+++ b/drivers/pci/dwc/pci-keystone.c
@@ -297,6 +297,7 @@ static const struct dw_pcie_host_ops keystone_pcie_host_ops = {
 	.msi_clear_irq = ks_dw_pcie_msi_clear_irq,
 	.get_msi_addr = ks_dw_pcie_get_msi_addr,
 	.msi_host_init = ks_dw_pcie_msi_host_init,
+	.msi_irq_ack = ks_dw_pcie_msi_irq_ack,
 	.scan_bus = ks_dw_pcie_v3_65_scan_bus,
 };
 
diff --git a/drivers/pci/dwc/pci-keystone.h b/drivers/pci/dwc/pci-keystone.h
index 30b7bc2..04e1366 100644
--- a/drivers/pci/dwc/pci-keystone.h
+++ b/drivers/pci/dwc/pci-keystone.h
@@ -53,9 +53,9 @@ int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
 		unsigned int devfn, int where, int size, u32 *val);
 void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie);
 void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie);
+void ks_dw_pcie_msi_irq_ack(int i, struct pcie_port *pp);
 void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq);
 void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq);
 void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp);
-int ks_dw_pcie_msi_host_init(struct pcie_port *pp,
-		struct msi_controller *chip);
+int ks_dw_pcie_msi_host_init(struct dw_pcie *pci, struct msi_controller *chip);
 int ks_dw_pcie_link_up(struct dw_pcie *pci);
diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
index 8f34c2f..cb9af93e3 100644
--- a/drivers/pci/dwc/pci-layerscape.c
+++ b/drivers/pci/dwc/pci-layerscape.c
@@ -185,10 +185,9 @@ static int ls1021_pcie_host_init(struct pcie_port *pp)
 	return ls_pcie_host_init(pp);
 }
 
-static int ls_pcie_msi_host_init(struct pcie_port *pp,
+static int ls_pcie_msi_host_init(struct dw_pcie *pci,
 				 struct msi_controller *chip)
 {
-	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 	struct device *dev = pci->dev;
 	struct device_node *np = dev->of_node;
 	struct device_node *msi_node;
diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
index 289d476..ee1c105 100644
--- a/drivers/pci/dwc/pcie-designware-host.c
+++ b/drivers/pci/dwc/pcie-designware-host.c
@@ -66,8 +66,20 @@ static void dw_msi_unmask_irq(struct irq_data *d)
 	irq_chip_unmask_parent(d);
 }
 
+static void dw_pci_ack_irq(struct irq_data *d)
+{
+	struct msi_desc *msi = irq_data_get_msi_desc(d);
+	struct pcie_port *pp;
+
+	pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
+
+	if (pp->ops->msi_irq_ack)
+		pp->ops->msi_irq_ack(d->irq, pp);
+}
+
 static struct irq_chip dw_pcie_msi_irq_chip = {
 	.name = "PCI-MSI",
+	.irq_ack = dw_pci_ack_irq,
 	.irq_mask = dw_msi_mask_irq,
 	.irq_unmask = dw_msi_unmask_irq,
 };
@@ -234,7 +246,7 @@ static int dw_pcie_irq_domain_alloc(struct irq_domain *domain,
 	for (i = 0; i < nr_irqs; i++)
 		irq_domain_set_info(domain, virq + i, bit + i,
 				    &dw_pci_msi_bottom_irq_chip,
-				    domain->host_data, handle_simple_irq,
+				    domain->host_data, handle_level_irq,
 				    NULL, NULL);
 
 	return 0;
@@ -619,11 +631,12 @@ int dw_pcie_host_init(struct pcie_port *pp)
 			if (ret)
 				goto error;
 
-			irq_set_chained_handler_and_data(pci->pp.msi_irq,
+			if (pp->msi_irq)
+				irq_set_chained_handler_and_data(pp->msi_irq,
 							 dw_chained_msi_isr,
 							 pci);
 		} else {
-			ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip);
+			ret = pp->ops->msi_host_init(pci, &dw_pcie_msi_chip);
 			if (ret < 0)
 				goto error;
 		}
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index 6178251..5294352 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -145,7 +145,8 @@ struct dw_pcie_host_ops {
 	u32 (*get_msi_data)(struct pcie_port *pp, int pos);
 	void (*scan_bus)(struct pcie_port *pp);
 	void (*set_num_vectors)(struct pcie_port *pp);
-	int (*msi_host_init)(struct pcie_port *pp, struct msi_controller *chip);
+	int (*msi_host_init)(struct dw_pcie *pci, struct msi_controller *chip);
+	void (*msi_irq_ack)(int irq, struct pcie_port *pp);
 };
 
 struct pcie_port {
-- 
2.7.4

[PATCH v3 8/9] pci: removing old irq api from pcie-designware

[Gustavo Pimentel]

This patch removes the old interrupt API.

Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
---
Change v1->v2:
- Nothing changed, just to follow the patch set version.
Change v2->v3:
- Nothing changed, just to follow the patch set version.

 drivers/pci/dwc/pci-keystone-dw.c      |   2 +-
 drivers/pci/dwc/pci-keystone.h         |   2 +-
 drivers/pci/dwc/pci-layerscape.c       |   3 +-
 drivers/pci/dwc/pcie-designware-host.c | 192 +--------------------------------
 drivers/pci/dwc/pcie-designware.h      |   2 +-
 5 files changed, 6 insertions(+), 195 deletions(-)

diff --git a/drivers/pci/dwc/pci-keystone-dw.c b/drivers/pci/dwc/pci-keystone-dw.c
index 4fe4ab3..16b7057 100644
--- a/drivers/pci/dwc/pci-keystone-dw.c
+++ b/drivers/pci/dwc/pci-keystone-dw.c
@@ -162,7 +162,7 @@ void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
 			 BIT(bit_pos));
 }
 
-int ks_dw_pcie_msi_host_init(struct dw_pcie *pci, struct msi_controller *chip)
+int ks_dw_pcie_msi_host_init(struct dw_pcie *pci)
 {
 	return dw_pcie_allocate_domains(pci);
 }
diff --git a/drivers/pci/dwc/pci-keystone.h b/drivers/pci/dwc/pci-keystone.h
index 04e1366..dad3894 100644
--- a/drivers/pci/dwc/pci-keystone.h
+++ b/drivers/pci/dwc/pci-keystone.h
@@ -57,5 +57,5 @@ void ks_dw_pcie_msi_irq_ack(int i, struct pcie_port *pp);
 void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq);
 void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq);
 void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp);
-int ks_dw_pcie_msi_host_init(struct dw_pcie *pci, struct msi_controller *chip);
+int ks_dw_pcie_msi_host_init(struct dw_pcie *pci);
 int ks_dw_pcie_link_up(struct dw_pcie *pci);
diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
index cb9af93e3..b246423 100644
--- a/drivers/pci/dwc/pci-layerscape.c
+++ b/drivers/pci/dwc/pci-layerscape.c
@@ -185,8 +185,7 @@ static int ls1021_pcie_host_init(struct pcie_port *pp)
 	return ls_pcie_host_init(pp);
 }
 
-static int ls_pcie_msi_host_init(struct dw_pcie *pci,
-				 struct msi_controller *chip)
+static int ls_pcie_msi_host_init(struct dw_pcie *pci)
 {
 	struct device *dev = pci->dev;
 	struct device_node *np = dev->of_node;
diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
index ee1c105..029a029 100644
--- a/drivers/pci/dwc/pcie-designware-host.c
+++ b/drivers/pci/dwc/pcie-designware-host.c
@@ -46,14 +46,6 @@ static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
 	return dw_pcie_write(pci->dbi_base + where, size, val);
 }
 
-static struct irq_chip dw_msi_irq_chip = {
-	.name = "PCI-MSI",
-	.irq_enable = pci_msi_unmask_irq,
-	.irq_disable = pci_msi_mask_irq,
-	.irq_mask = pci_msi_mask_irq,
-	.irq_unmask = pci_msi_unmask_irq,
-};
-
 static void dw_msi_mask_irq(struct irq_data *d)
 {
 	pci_msi_mask_irq(d);
@@ -317,186 +309,6 @@ void dw_pcie_msi_init(struct pcie_port *pp)
 			    upper_32_bits(msi_target));
 }
 
-static void dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
-{
-	unsigned int res, bit, ctrl;
-
-	ctrl = irq / 32;
-	res = ctrl * 12;
-	bit = irq % 32;
-	pp->irq_status[ctrl] &= ~(1 << bit);
-	dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4,
-			    pp->irq_status[ctrl]);
-}
-
-static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
-			    unsigned int nvec, unsigned int pos)
-{
-	unsigned int i;
-
-	for (i = 0; i < nvec; i++) {
-		irq_set_msi_desc_off(irq_base, i, NULL);
-		/* Disable corresponding interrupt on MSI controller */
-		if (pp->ops->msi_clear_irq)
-			pp->ops->msi_clear_irq(pp, pos + i);
-		else
-			dw_pcie_msi_clear_irq(pp, pos + i);
-	}
-
-	bitmap_release_region(pp->msi_irq_in_use, pos, order_base_2(nvec));
-}
-
-static void dw_pcie_msi_set_irq(struct pcie_port *pp, int irq)
-{
-	unsigned int res, bit, ctrl;
-
-	ctrl = irq / 32;
-	res = ctrl * 12;
-	bit = irq % 32;
-	pp->irq_status[ctrl] |= 1 << bit;
-	dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4,
-			    pp->irq_status[ctrl]);
-}
-
-static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
-{
-	int irq, pos0, i;
-	struct pcie_port *pp;
-
-	pp = (struct pcie_port *)msi_desc_to_pci_sysdata(desc);
-	pos0 = bitmap_find_free_region(pp->msi_irq_in_use, MAX_MSI_IRQS,
-				       order_base_2(no_irqs));
-	if (pos0 < 0)
-		goto no_valid_irq;
-
-	irq = irq_find_mapping(pp->irq_domain, pos0);
-	if (!irq)
-		goto no_valid_irq;
-
-	/*
-	 * irq_create_mapping (called from dw_pcie_host_init) pre-allocates
-	 * descs so there is no need to allocate descs here. We can therefore
-	 * assume that if irq_find_mapping above returns non-zero, then the
-	 * descs are also successfully allocated.
-	 */
-
-	for (i = 0; i < no_irqs; i++) {
-		if (irq_set_msi_desc_off(irq, i, desc) != 0) {
-			clear_irq_range(pp, irq, i, pos0);
-			goto no_valid_irq;
-		}
-		/*Enable corresponding interrupt in MSI interrupt controller */
-		if (pp->ops->msi_set_irq)
-			pp->ops->msi_set_irq(pp, pos0 + i);
-		else
-			dw_pcie_msi_set_irq(pp, pos0 + i);
-	}
-
-	*pos = pos0;
-	desc->nvec_used = no_irqs;
-	desc->msi_attrib.multiple = order_base_2(no_irqs);
-
-	return irq;
-
-no_valid_irq:
-	*pos = pos0;
-	return -ENOSPC;
-}
-
-static void dw_msi_setup_msg(struct pcie_port *pp, unsigned int irq, u32 pos)
-{
-	struct msi_msg msg;
-	u64 msi_target;
-
-	if (pp->ops->get_msi_addr)
-		msi_target = pp->ops->get_msi_addr(pp);
-	else
-		msi_target = virt_to_phys((void *)pp->msi_data);
-
-	msg.address_lo = (u32)(msi_target & 0xffffffff);
-	msg.address_hi = (u32)(msi_target >> 32 & 0xffffffff);
-
-	if (pp->ops->get_msi_data)
-		msg.data = pp->ops->get_msi_data(pp, pos);
-	else
-		msg.data = pos;
-
-	pci_write_msi_msg(irq, &msg);
-}
-
-static int dw_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
-			    struct msi_desc *desc)
-{
-	int irq, pos;
-	struct pcie_port *pp = pdev->bus->sysdata;
-
-	if (desc->msi_attrib.is_msix)
-		return -EINVAL;
-
-	irq = assign_irq(1, desc, &pos);
-	if (irq < 0)
-		return irq;
-
-	dw_msi_setup_msg(pp, irq, pos);
-
-	return 0;
-}
-
-static int dw_msi_setup_irqs(struct msi_controller *chip, struct pci_dev *pdev,
-			     int nvec, int type)
-{
-#ifdef CONFIG_PCI_MSI
-	int irq, pos;
-	struct msi_desc *desc;
-	struct pcie_port *pp = pdev->bus->sysdata;
-
-	/* MSI-X interrupts are not supported */
-	if (type == PCI_CAP_ID_MSIX)
-		return -EINVAL;
-
-	WARN_ON(!list_is_singular(&pdev->dev.msi_list));
-	desc = list_entry(pdev->dev.msi_list.next, struct msi_desc, list);
-
-	irq = assign_irq(nvec, desc, &pos);
-	if (irq < 0)
-		return irq;
-
-	dw_msi_setup_msg(pp, irq, pos);
-
-	return 0;
-#else
-	return -EINVAL;
-#endif
-}
-
-static void dw_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
-{
-	struct irq_data *data = irq_get_irq_data(irq);
-	struct msi_desc *msi = irq_data_get_msi_desc(data);
-	struct pcie_port *pp = (struct pcie_port *)msi_desc_to_pci_sysdata(msi);
-
-	clear_irq_range(pp, irq, 1, data->hwirq);
-}
-
-static struct msi_controller dw_pcie_msi_chip = {
-	.setup_irq = dw_msi_setup_irq,
-	.setup_irqs = dw_msi_setup_irqs,
-	.teardown_irq = dw_msi_teardown_irq,
-};
-
-static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
-			   irq_hw_number_t hwirq)
-{
-	irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq);
-	irq_set_chip_data(irq, domain->host_data);
-
-	return 0;
-}
-
-static const struct irq_domain_ops msi_domain_ops = {
-	.map = dw_pcie_msi_map,
-};
-
 int dw_pcie_host_init(struct pcie_port *pp)
 {
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
@@ -507,7 +319,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
 	struct pci_bus *bus, *child;
 	struct pci_host_bridge *bridge;
 	struct resource *cfg_res;
-	int i, ret;
+	int ret;
 
 	spin_lock_init(&pci->pp.lock);
 
@@ -636,7 +448,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
 							 dw_chained_msi_isr,
 							 pci);
 		} else {
-			ret = pp->ops->msi_host_init(pci, &dw_pcie_msi_chip);
+			ret = pp->ops->msi_host_init(pci);
 			if (ret < 0)
 				goto error;
 		}
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index 5294352..c4b9c11 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -145,7 +145,7 @@ struct dw_pcie_host_ops {
 	u32 (*get_msi_data)(struct pcie_port *pp, int pos);
 	void (*scan_bus)(struct pcie_port *pp);
 	void (*set_num_vectors)(struct pcie_port *pp);
-	int (*msi_host_init)(struct dw_pcie *pci, struct msi_controller *chip);
+	int (*msi_host_init)(struct dw_pcie *pci);
 	void (*msi_irq_ack)(int irq, struct pcie_port *pp);
 };
 
-- 
2.7.4

[PATCH v3 9/9] pci: remove limitation of the number of the available IRQs

[Gustavo Pimentel]

The Synopsys PCIe Controller supports up to 256 IRQs distributed by 8
controller registers.
Having this in mind, the number of the maximum number of IRQs was changed
to 256 and now the number of controllers is calculated based on the number
of vectors used by the specific SoC driver.

Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
---
Change v1->v2:
- New patch.
Change v2->v3:
- Nothing changed, just to follow the patch set version.

 drivers/pci/dwc/pcie-designware-host.c | 12 ++++++++----
 drivers/pci/dwc/pcie-designware.h      | 10 +++-------
 2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
index 029a029..49c9c25 100644
--- a/drivers/pci/dwc/pcie-designware-host.c
+++ b/drivers/pci/dwc/pcie-designware-host.c
@@ -85,11 +85,13 @@ static struct msi_domain_info dw_pcie_msi_domain_info = {
 /* MSI int handler */
 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
 {
-	u32 val;
 	int i, pos, irq;
+	u32 val, num_ctrls;
 	irqreturn_t ret = IRQ_NONE;
 
-	for (i = 0; i < MAX_MSI_CTRLS; i++) {
+	num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
+
+	for (i = 0; i < num_ctrls; i++) {
 		dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
 				    &val);
 		if (!val)
@@ -636,13 +638,15 @@ static u8 dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
 
 void dw_pcie_setup_rc(struct pcie_port *pp)
 {
-	u32 val, ctrl;
+	u32 val, ctrl, num_ctrls;
 	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 
 	dw_pcie_setup(pci);
 
+	num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
+
 	/* Initialize IRQ Status array */
-	for (ctrl = 0; ctrl < MAX_MSI_CTRLS; ctrl++)
+	for (ctrl = 0; ctrl < num_ctrls; ctrl++)
 		dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + (ctrl * 12), 4,
 				    &pp->irq_status[ctrl]);
 	/* setup RC BARs */
diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
index c4b9c11..343db0c 100644
--- a/drivers/pci/dwc/pcie-designware.h
+++ b/drivers/pci/dwc/pcie-designware.h
@@ -105,13 +105,9 @@
 #define MSI_MESSAGE_ADDR_L32		0x54
 #define MSI_MESSAGE_ADDR_U32		0x58
 
-/*
- * Maximum number of MSI IRQs can be 256 per controller. But keep
- * it 32 as of now. Probably we will never need more than 32. If needed,
- * then increment it in multiple of 32.
- */
-#define MAX_MSI_IRQS			32
-#define MAX_MSI_CTRLS			(MAX_MSI_IRQS / 32)
+#define MAX_MSI_IRQS			256
+#define MAX_MSI_IRQS_PER_CTRL		32
+#define MAX_MSI_CTRLS			(MAX_MSI_IRQS / MAX_MSI_IRQS_PER_CTRL)
 #define MSI_DEF_NUM_VECTORS		32
 
 struct pcie_port;
-- 
2.7.4

Re: [PATCH v3 7/9] pci: keystone SoC driver adapted to new irq API

[Kishon Vijay Abraham I]

Hi Gustavo,

On Thursday 28 December 2017 05:26 PM, Gustavo Pimentel wrote:
> This patch adapts Keystone SoC specific driver to use the new interrupt api
> available in pcie-designware. A new callback was added to dw_pcie_host_ops
> to handle a specific Keystone function and msi_host_init callback is
> changed to simplify the access to pci data structure for keystone all SoC
> drivers that use the structure.
> 
> Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
> ---
> Change v1->v2:
> - Removed hardcoded num_vectors configuration (now it is done in the core driver by default)
> Change v2->v3:
> - 
> 
> 
> 
> 
> 
>  drivers/pci/dwc/pci-keystone-dw.c      | 88 ++--------------------------------
>  drivers/pci/dwc/pci-keystone.c         |  1 +
>  drivers/pci/dwc/pci-keystone.h         |  4 +-
>  drivers/pci/dwc/pci-layerscape.c       |  3 +-
>  drivers/pci/dwc/pcie-designware-host.c | 19 ++++++--
>  drivers/pci/dwc/pcie-designware.h      |  3 +-

The designware specific patches should be part of
"[1/9] pci: adding new irq api to pci-designware"

Also layerscap is not related to $subject.

Thanks
Kishon

Re: [PATCH v3 7/9] pci: keystone SoC driver adapted to new irq API

[Jingoo Han]

On Thursday, December 28, 2017 7:44 AM, Kishon Vijay Abraham I wrote:
> 
> Hi Gustavo,
> 
> On Thursday 28 December 2017 05:26 PM, Gustavo Pimentel wrote:
> > This patch adapts Keystone SoC specific driver to use the new interrupt
> api
> > available in pcie-designware. A new callback was added to
> dw_pcie_host_ops
> > to handle a specific Keystone function and msi_host_init callback is
> > changed to simplify the access to pci data structure for keystone all
> SoC
> > drivers that use the structure.
> >
> > Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
> > ---
> > Change v1->v2:
> > - Removed hardcoded num_vectors configuration (now it is done in the
> core driver by default)
> > Change v2->v3:
> > -
> >
> >
> >
> >
> >
> >  drivers/pci/dwc/pci-keystone-dw.c      | 88
++---------------------------
> -----
> >  drivers/pci/dwc/pci-keystone.c         |  1 +
> >  drivers/pci/dwc/pci-keystone.h         |  4 +-
> >  drivers/pci/dwc/pci-layerscape.c       |  3 +-
> >  drivers/pci/dwc/pcie-designware-host.c | 19 ++++++--
> >  drivers/pci/dwc/pcie-designware.h      |  3 +-
> 
> The designware specific patches should be part of
> "[1/9] pci: adding new irq api to pci-designware"
> 
> Also layerscap is not related to $subject.

Yes, right.

To Gustavo,
Please split this patch to two patches. 

> 
> Thanks
> Kishon

Re: [PATCH v3 0/9] add new irq api to pcie-designware

[Bjorn Helgaas]

On Thu, Dec 28, 2017 at 11:56:38AM +0000, Gustavo Pimentel wrote:
> This patch series adds the new interrupt api to pcie-designware make it
> possible to use features like MSIX.
> The work consisted of adapting the pcie-designware-host and each SoC
> specific driver.
> The patch set was made against the Bjorn' next branch.
> A new patch set (v3) was created that includes Kishon's fixes (pci end
> point error and a dra7xx warning) in file
> 0007-pci-keystone-SoC-driver-adapted-to-new-irq-API.patch.
> 
> Gustavo Pimentel (9):
>   pci: adding new irq api to pci-designware
>   pci: exynos SoC driver adapted to new irq API
>   pci: imx6 SoC driver adapted to new irq API
>   pci: artpec6 SoC driver adapted to new irq API
>   pci: generic PCIe DW driver adapted to new irq API
>   pci: qcom SoC driver adapted to new irq API
>   pci: keystone SoC driver adapted to new irq API
>   pci: removing old irq api from pcie-designware
>   pci: remove limitation of the number of the available IRQs

Please update the summary lines to match the drivers/pci conventions:

  PCI: dwc: Add new IRQ API
  PCI: dwc: exynos: Adapt to new IRQ API
  PCI: dwc: imx6: Adapt to new IRQ API
  PCI: dwc: artpec6: Adapt to new IRQ API
  PCI: dwc: designware: Adapt to new IRQ API
  PCI: dwc: qcom: Adapt to new IRQ API
  PCI: dwc: keystone: Adapt to new IRQ API
  PCI: dwc: Remove old IRQ API
  PCI: dwc: Remove limitation on number of IRQs

The first patch summary should contain more information than "Add new
IRQ API".  That summary doesn't tell us anything about what is new or
why we want it.  Even the changelog doesn't contain that information.

Please also update the changelogs to consistently capitalize IRQ, API,
etc.  It's currently a mix, which is distracting to read.

Also, instead of saying "This patch adds the ...", simply say "Add the
...".  The "This patch" context is obvious since the changelog is an
integral part of the commit.

Please use blank lines to separate paragraphs.

>  drivers/pci/dwc/pci-exynos.c           |  18 --
>  drivers/pci/dwc/pci-imx6.c             |  18 --
>  drivers/pci/dwc/pci-keystone-dw.c      |  88 +-------
>  drivers/pci/dwc/pci-keystone.c         |   1 +
>  drivers/pci/dwc/pci-keystone.h         |   4 +-
>  drivers/pci/dwc/pci-layerscape.c       |   4 +-
>  drivers/pci/dwc/pcie-artpec6.c         |  18 --
>  drivers/pci/dwc/pcie-designware-host.c | 391 +++++++++++++++++++--------------
>  drivers/pci/dwc/pcie-designware-plat.c |  16 --
>  drivers/pci/dwc/pcie-designware.h      |  30 ++-
>  drivers/pci/dwc/pcie-qcom.c            |  16 --
>  11 files changed, 254 insertions(+), 350 deletions(-)
> 
> -- 
> 2.7.4
> 
> 

Re: [PATCH v3 7/9] pci: keystone SoC driver adapted to new irq API

[Gustavo Pimentel]

Hi Jingoo and Kishon,

On 28/12/2017 16:13, Jingoo Han wrote:
> On Thursday, December 28, 2017 7:44 AM, Kishon Vijay Abraham I wrote:
>>
>> Hi Gustavo,
>>
>> On Thursday 28 December 2017 05:26 PM, Gustavo Pimentel wrote:
>>> This patch adapts Keystone SoC specific driver to use the new interrupt
>> api
>>> available in pcie-designware. A new callback was added to
>> dw_pcie_host_ops
>>> to handle a specific Keystone function and msi_host_init callback is
>>> changed to simplify the access to pci data structure for keystone all
>> SoC
>>> drivers that use the structure.
>>>
>>> Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
>>> ---
>>> Change v1->v2:
>>> - Removed hardcoded num_vectors configuration (now it is done in the
>> core driver by default)
>>> Change v2->v3:
>>> -
>>>
>>>
>>>
>>>
>>>
>>>  drivers/pci/dwc/pci-keystone-dw.c      | 88
> ++---------------------------
>> -----
>>>  drivers/pci/dwc/pci-keystone.c         |  1 +
>>>  drivers/pci/dwc/pci-keystone.h         |  4 +-
>>>  drivers/pci/dwc/pci-layerscape.c       |  3 +-
>>>  drivers/pci/dwc/pcie-designware-host.c | 19 ++++++--
>>>  drivers/pci/dwc/pcie-designware.h      |  3 +-
>>
>> The designware specific patches should be part of
>> "[1/9] pci: adding new irq api to pci-designware"

Ok, I will move your (Kishon) fixes to the 0001 patch file, no problem.

>>
>> Also layerscap is not related to $subject.

Please note there are some initial changes on this patch (maybe they could be in
a isolated patch) related to pci-layerscape.c, pcie-designware-host.c and
pcie-designware.h files that changes the msi_host_init callback signature and
this affects the Keystone, Layerscape drivers and the core at the same time,
that's the reason why this modification touches on these three files and should
be together.
Was I able to pass this information clearly?

> 
> Yes, right.
> 
> To Gustavo,
> Please split this patch to two patches. 

If both agree I can split this patch, by the reason described before, OK?

> 
>>
>> Thanks
>> Kishon
> 

Re: [PATCH v3 1/9] pci: adding new irq api to pci-designware

[Kishon Vijay Abraham I]

Hi Gustavo,

On Thursday 28 December 2017 05:26 PM, Gustavo Pimentel wrote:
> This patch adds the new interrupt api to pcie-designware, keeping the old
> one. Although the old API is still available, pcie-designware initiates
> with the new one.
> 
> Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
> ---
> Change v1->v2:
> - num_vectors is now not configurable by DT. Now it is 32 by default and
> can be overridden by any specific SoC driver.
> Change v2->v3:
> - Nothing changed, just to follow the patch set version.
> 
>  drivers/pci/dwc/pcie-designware-host.c | 282 +++++++++++++++++++++++++++++----
>  drivers/pci/dwc/pcie-designware.h      |  17 ++
>  2 files changed, 272 insertions(+), 27 deletions(-)
> 
> diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
> index 81e2157..289d476 100644
> --- a/drivers/pci/dwc/pcie-designware-host.c
> +++ b/drivers/pci/dwc/pcie-designware-host.c
> @@ -11,6 +11,7 @@
>   * published by the Free Software Foundation.
>   */
>  
> +#include <linux/irqchip/chained_irq.h>
>  #include <linux/irqdomain.h>
>  #include <linux/of_address.h>
>  #include <linux/of_pci.h>
> @@ -53,6 +54,30 @@ static struct irq_chip dw_msi_irq_chip = {
>  	.irq_unmask = pci_msi_unmask_irq,
>  };
>  
> +static void dw_msi_mask_irq(struct irq_data *d)
> +{
> +	pci_msi_mask_irq(d);
> +	irq_chip_mask_parent(d);
> +}
> +
> +static void dw_msi_unmask_irq(struct irq_data *d)
> +{
> +	pci_msi_unmask_irq(d);
> +	irq_chip_unmask_parent(d);
> +}
> +
> +static struct irq_chip dw_pcie_msi_irq_chip = {
> +	.name = "PCI-MSI",
> +	.irq_mask = dw_msi_mask_irq,
> +	.irq_unmask = dw_msi_unmask_irq,
> +};
> +
> +static struct msi_domain_info dw_pcie_msi_domain_info = {
> +	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
> +		     MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
> +	.chip	= &dw_pcie_msi_irq_chip,
> +};
> +
>  /* MSI int handler */
>  irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
>  {
> @@ -81,6 +106,191 @@ irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
>  	return ret;
>  }
>  
> +/* Chained MSI interrupt service routine */
> +static void dw_chained_msi_isr(struct irq_desc *desc)
> +{
> +	struct irq_chip *chip = irq_desc_get_chip(desc);
> +	struct pcie_port *pp;
> +	struct dw_pcie *pci;
> +
> +	chained_irq_enter(chip, desc);
> +	pci = irq_desc_get_handler_data(desc);
> +	pp = &pci->pp;
> +
> +	dw_handle_msi_irq(pp);
> +
> +	chained_irq_exit(chip, desc);
> +}
> +
> +static void dw_pci_setup_msi_msg(struct irq_data *data, struct msi_msg *msg)
> +{
> +	struct dw_pcie *pci = irq_data_get_irq_chip_data(data);
> +	struct pcie_port *pp = &pci->pp;
> +	u64 msi_target;
> +
> +	if (pp->ops->get_msi_addr)
> +		msi_target = pp->ops->get_msi_addr(pp);
> +	else
> +		msi_target = virt_to_phys((void *)pp->msi_data);
> +
> +	msg->address_lo = lower_32_bits(msi_target);
> +	msg->address_hi = upper_32_bits(msi_target);
> +
> +	if (pp->ops->get_msi_data)
> +		msg->data = pp->ops->get_msi_data(pp, data->hwirq);
> +	else
> +		msg->data = data->hwirq;
> +
> +	dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n",
> +		(int)data->hwirq, msg->address_hi, msg->address_lo);
> +}
> +
> +static int dw_pci_msi_set_affinity(struct irq_data *irq_data,
> +				   const struct cpumask *mask, bool force)
> +{
> +	return -EINVAL;
> +}
> +
> +static void dw_pci_bottom_mask(struct irq_data *data)
> +{
> +	struct dw_pcie *pci = irq_data_get_irq_chip_data(data);
> +	struct pcie_port *pp = &pci->pp;
> +	unsigned int res, bit, ctrl;
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&pp->lock, flags);
> +
> +	if (pp->ops->msi_clear_irq)
> +		pp->ops->msi_clear_irq(pp, data->hwirq);
> +	else {
> +		ctrl = data->hwirq / 32;
> +		res = ctrl * 12;
> +		bit = data->hwirq % 32;
> +
> +		pp->irq_status[ctrl] &= ~(1 << bit);
> +		dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4,
> +				    pp->irq_status[ctrl]);
> +	}
> +
> +	spin_unlock_irqrestore(&pp->lock, flags);
> +}
> +
> +static void dw_pci_bottom_unmask(struct irq_data *data)
> +{
> +	struct dw_pcie *pci = irq_data_get_irq_chip_data(data);
> +	struct pcie_port *pp = &pci->pp;
> +	unsigned int res, bit, ctrl;
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&pp->lock, flags);
> +
> +	if (pp->ops->msi_set_irq)
> +		pp->ops->msi_set_irq(pp, data->hwirq);
> +	else {
> +		ctrl = data->hwirq / 32;
> +		res = ctrl * 12;
> +		bit = data->hwirq % 32;
> +
> +		pp->irq_status[ctrl] |= 1 << bit;
> +		dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4,
> +				    pp->irq_status[ctrl]);
> +	}
> +
> +	spin_unlock_irqrestore(&pp->lock, flags);
> +}
> +
> +static struct irq_chip dw_pci_msi_bottom_irq_chip = {
> +	.name = "DWPCI-MSI",
> +	.irq_compose_msi_msg = dw_pci_setup_msi_msg,
> +	.irq_set_affinity = dw_pci_msi_set_affinity,
> +	.irq_mask = dw_pci_bottom_mask,
> +	.irq_unmask = dw_pci_bottom_unmask,
> +};
> +
> +static int dw_pcie_irq_domain_alloc(struct irq_domain *domain,
> +				    unsigned int virq, unsigned int nr_irqs,
> +				    void *args)
> +{
> +	struct dw_pcie *pci = domain->host_data;
> +	struct pcie_port *pp = &pci->pp;
> +	unsigned long flags;
> +	unsigned long bit;
> +	u32 i;
> +
> +	spin_lock_irqsave(&pp->lock, flags);
> +
> +	bit = bitmap_find_next_zero_area(pp->msi_irq_in_use, pp->num_vectors, 0,
> +					 nr_irqs, 0);
> +
> +	if (bit >= pp->num_vectors) {
> +		spin_unlock_irqrestore(&pp->lock, flags);
> +		return -ENOSPC;
> +	}
> +
> +	bitmap_set(pp->msi_irq_in_use, bit, nr_irqs);
> +
> +	spin_unlock_irqrestore(&pp->lock, flags);
> +
> +	for (i = 0; i < nr_irqs; i++)
> +		irq_domain_set_info(domain, virq + i, bit + i,
> +				    &dw_pci_msi_bottom_irq_chip,
> +				    domain->host_data, handle_simple_irq,
> +				    NULL, NULL);
> +
> +	return 0;
> +}
> +
> +static void dw_pcie_irq_domain_free(struct irq_domain *domain,
> +				    unsigned int virq, unsigned int nr_irqs)
> +{
> +	struct irq_data *data = irq_domain_get_irq_data(domain, virq);
> +	struct dw_pcie *pci = irq_data_get_irq_chip_data(data);
> +	struct pcie_port *pp = &pci->pp;
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&pp->lock, flags);
> +	bitmap_clear(pp->msi_irq_in_use, data->hwirq, nr_irqs);
> +	spin_unlock_irqrestore(&pp->lock, flags);
> +}
> +
> +static const struct irq_domain_ops dw_pcie_msi_domain_ops = {
> +	.alloc	= dw_pcie_irq_domain_alloc,
> +	.free	= dw_pcie_irq_domain_free,
> +};
> +
> +int dw_pcie_allocate_domains(struct dw_pcie *pci)
> +{

Since this function is specific to host mode, the preferred argument should be
struct pcie_port *pp.

> +	struct pcie_port *pp = &pci->pp;
> +	struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node);
> +
> +	pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors,
> +					       &dw_pcie_msi_domain_ops, pci);

pp can be directly passed as host_data so that getting pp again back from pci
can be avoided in all the above functions.

Thanks
Kishon

Re: [PATCH v3 7/9] pci: keystone SoC driver adapted to new irq API

[Kishon Vijay Abraham I]

Hi Gustavo,

On Thursday 28 December 2017 05:26 PM, Gustavo Pimentel wrote:
> This patch adapts Keystone SoC specific driver to use the new interrupt api
> available in pcie-designware. A new callback was added to dw_pcie_host_ops
> to handle a specific Keystone function and msi_host_init callback is
> changed to simplify the access to pci data structure for keystone all SoC
> drivers that use the structure.
> 
> Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
> ---
> Change v1->v2:
> - Removed hardcoded num_vectors configuration (now it is done in the core driver by default)
> Change v2->v3:
> - 
> 
> 
> 
> 
> 
>  drivers/pci/dwc/pci-keystone-dw.c      | 88 ++--------------------------------
>  drivers/pci/dwc/pci-keystone.c         |  1 +
>  drivers/pci/dwc/pci-keystone.h         |  4 +-
>  drivers/pci/dwc/pci-layerscape.c       |  3 +-
>  drivers/pci/dwc/pcie-designware-host.c | 19 ++++++--
>  drivers/pci/dwc/pcie-designware.h      |  3 +-
>  6 files changed, 26 insertions(+), 92 deletions(-)
> 
> diff --git a/drivers/pci/dwc/pci-keystone-dw.c b/drivers/pci/dwc/pci-keystone-dw.c
> index 2fb20b8..4fe4ab3 100644
> --- a/drivers/pci/dwc/pci-keystone-dw.c
> +++ b/drivers/pci/dwc/pci-keystone-dw.c
> @@ -124,19 +124,15 @@ void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset)
>  	}
>  }
>  
> -static void ks_dw_pcie_msi_irq_ack(struct irq_data *d)
> +void ks_dw_pcie_msi_irq_ack(int irq, struct pcie_port *pp)
>  {
>  	u32 offset, reg_offset, bit_pos;
>  	struct keystone_pcie *ks_pcie;
> -	struct msi_desc *msi;
> -	struct pcie_port *pp;
>  	struct dw_pcie *pci;
>  
> -	msi = irq_data_get_msi_desc(d);
> -	pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
>  	pci = to_dw_pcie_from_pp(pp);
>  	ks_pcie = to_keystone_pcie(pci);
> -	offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
> +	offset = irq - irq_linear_revmap(pp->irq_domain, 0);
>  	update_reg_offset_bit_pos(offset, &reg_offset, &bit_pos);
>  
>  	ks_dw_app_writel(ks_pcie, MSI0_IRQ_STATUS + (reg_offset << 4),
> @@ -166,85 +162,9 @@ void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
>  			 BIT(bit_pos));
>  }
>  
> -static void ks_dw_pcie_msi_irq_mask(struct irq_data *d)
> +int ks_dw_pcie_msi_host_init(struct dw_pcie *pci, struct msi_controller *chip)
>  {
> -	struct msi_desc *msi;
> -	struct pcie_port *pp;
> -	u32 offset;
> -
> -	msi = irq_data_get_msi_desc(d);
> -	pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
> -	offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
> -
> -	/* Mask the end point if PVM implemented */
> -	if (IS_ENABLED(CONFIG_PCI_MSI)) {
> -		if (msi->msi_attrib.maskbit)
> -			pci_msi_mask_irq(d);
> -	}
> -
> -	ks_dw_pcie_msi_clear_irq(pp, offset);
> -}
> -
> -static void ks_dw_pcie_msi_irq_unmask(struct irq_data *d)
> -{
> -	struct msi_desc *msi;
> -	struct pcie_port *pp;
> -	u32 offset;
> -
> -	msi = irq_data_get_msi_desc(d);
> -	pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
> -	offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
> -
> -	/* Mask the end point if PVM implemented */
> -	if (IS_ENABLED(CONFIG_PCI_MSI)) {
> -		if (msi->msi_attrib.maskbit)
> -			pci_msi_unmask_irq(d);
> -	}
> -
> -	ks_dw_pcie_msi_set_irq(pp, offset);
> -}
> -
> -static struct irq_chip ks_dw_pcie_msi_irq_chip = {
> -	.name = "Keystone-PCIe-MSI-IRQ",
> -	.irq_ack = ks_dw_pcie_msi_irq_ack,
> -	.irq_mask = ks_dw_pcie_msi_irq_mask,
> -	.irq_unmask = ks_dw_pcie_msi_irq_unmask,
> -};
> -
> -static int ks_dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
> -			      irq_hw_number_t hwirq)
> -{
> -	irq_set_chip_and_handler(irq, &ks_dw_pcie_msi_irq_chip,
> -				 handle_level_irq);
> -	irq_set_chip_data(irq, domain->host_data);
> -
> -	return 0;
> -}
> -
> -static const struct irq_domain_ops ks_dw_pcie_msi_domain_ops = {
> -	.map = ks_dw_pcie_msi_map,
> -};
> -
> -int ks_dw_pcie_msi_host_init(struct pcie_port *pp, struct msi_controller *chip)
> -{
> -	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> -	struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
> -	struct device *dev = pci->dev;
> -	int i;
> -
> -	pp->irq_domain = irq_domain_add_linear(ks_pcie->msi_intc_np,
> -					MAX_MSI_IRQS,
> -					&ks_dw_pcie_msi_domain_ops,
> -					chip);
> -	if (!pp->irq_domain) {
> -		dev_err(dev, "irq domain init failed\n");
> -		return -ENXIO;
> -	}
> -
> -	for (i = 0; i < MAX_MSI_IRQS; i++)
> -		irq_create_mapping(pp->irq_domain, i);
> -
> -	return 0;
> +	return dw_pcie_allocate_domains(pci);
>  }
>  
>  void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie)
> diff --git a/drivers/pci/dwc/pci-keystone.c b/drivers/pci/dwc/pci-keystone.c
> index 5bee3af..76901fa 100644
> --- a/drivers/pci/dwc/pci-keystone.c
> +++ b/drivers/pci/dwc/pci-keystone.c
> @@ -297,6 +297,7 @@ static const struct dw_pcie_host_ops keystone_pcie_host_ops = {
>  	.msi_clear_irq = ks_dw_pcie_msi_clear_irq,
>  	.get_msi_addr = ks_dw_pcie_get_msi_addr,
>  	.msi_host_init = ks_dw_pcie_msi_host_init,
> +	.msi_irq_ack = ks_dw_pcie_msi_irq_ack,
>  	.scan_bus = ks_dw_pcie_v3_65_scan_bus,
>  };
>  
> diff --git a/drivers/pci/dwc/pci-keystone.h b/drivers/pci/dwc/pci-keystone.h
> index 30b7bc2..04e1366 100644
> --- a/drivers/pci/dwc/pci-keystone.h
> +++ b/drivers/pci/dwc/pci-keystone.h
> @@ -53,9 +53,9 @@ int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
>  		unsigned int devfn, int where, int size, u32 *val);
>  void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie);
>  void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie);
> +void ks_dw_pcie_msi_irq_ack(int i, struct pcie_port *pp);
>  void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq);
>  void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq);
>  void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp);
> -int ks_dw_pcie_msi_host_init(struct pcie_port *pp,
> -		struct msi_controller *chip);
> +int ks_dw_pcie_msi_host_init(struct dw_pcie *pci, struct msi_controller *chip);
>  int ks_dw_pcie_link_up(struct dw_pcie *pci);
> diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
> index 8f34c2f..cb9af93e3 100644
> --- a/drivers/pci/dwc/pci-layerscape.c
> +++ b/drivers/pci/dwc/pci-layerscape.c
> @@ -185,10 +185,9 @@ static int ls1021_pcie_host_init(struct pcie_port *pp)
>  	return ls_pcie_host_init(pp);
>  }
>  
> -static int ls_pcie_msi_host_init(struct pcie_port *pp,
> +static int ls_pcie_msi_host_init(struct dw_pcie *pci,
>  				 struct msi_controller *chip)
>  {
> -	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>  	struct device *dev = pci->dev;
>  	struct device_node *np = dev->of_node;
>  	struct device_node *msi_node;
> diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
> index 289d476..ee1c105 100644
> --- a/drivers/pci/dwc/pcie-designware-host.c
> +++ b/drivers/pci/dwc/pcie-designware-host.c
> @@ -66,8 +66,20 @@ static void dw_msi_unmask_irq(struct irq_data *d)
>  	irq_chip_unmask_parent(d);
>  }
>  
> +static void dw_pci_ack_irq(struct irq_data *d)
> +{
> +	struct msi_desc *msi = irq_data_get_msi_desc(d);
> +	struct pcie_port *pp;
> +
> +	pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
> +
> +	if (pp->ops->msi_irq_ack)
> +		pp->ops->msi_irq_ack(d->irq, pp);
> +}
> +
>  static struct irq_chip dw_pcie_msi_irq_chip = {
>  	.name = "PCI-MSI",
> +	.irq_ack = dw_pci_ack_irq,
>  	.irq_mask = dw_msi_mask_irq,
>  	.irq_unmask = dw_msi_unmask_irq,
>  };
> @@ -234,7 +246,7 @@ static int dw_pcie_irq_domain_alloc(struct irq_domain *domain,
>  	for (i = 0; i < nr_irqs; i++)
>  		irq_domain_set_info(domain, virq + i, bit + i,
>  				    &dw_pci_msi_bottom_irq_chip,
> -				    domain->host_data, handle_simple_irq,
> +				    domain->host_data, handle_level_irq,
>  				    NULL, NULL);
>  
>  	return 0;
> @@ -619,11 +631,12 @@ int dw_pcie_host_init(struct pcie_port *pp)
>  			if (ret)
>  				goto error;
>  
> -			irq_set_chained_handler_and_data(pci->pp.msi_irq,
> +			if (pp->msi_irq)
> +				irq_set_chained_handler_and_data(pp->msi_irq,
>  							 dw_chained_msi_isr,
>  							 pci);
>  		} else {
> -			ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip);
> +			ret = pp->ops->msi_host_init(pci, &dw_pcie_msi_chip);
>  			if (ret < 0)
>  				goto error;
>  		}
> diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
> index 6178251..5294352 100644
> --- a/drivers/pci/dwc/pcie-designware.h
> +++ b/drivers/pci/dwc/pcie-designware.h
> @@ -145,7 +145,8 @@ struct dw_pcie_host_ops {
>  	u32 (*get_msi_data)(struct pcie_port *pp, int pos);
>  	void (*scan_bus)(struct pcie_port *pp);
>  	void (*set_num_vectors)(struct pcie_port *pp);
> -	int (*msi_host_init)(struct pcie_port *pp, struct msi_controller *chip);
> +	int (*msi_host_init)(struct dw_pcie *pci, struct msi_controller *chip);

I'd prefer the signature is maintained since msi_host_init being a host
specific callback, it makes sense to have "struct pcie_port *pp".

Thanks
Kishon

Re: [PATCH v3 7/9] pci: keystone SoC driver adapted to new irq API

[Kishon Vijay Abraham I]

Hi Gustavo,

On Friday 29 December 2017 03:03 PM, Gustavo Pimentel wrote:
> Hi Jingoo and Kishon,
> 
> On 28/12/2017 16:13, Jingoo Han wrote:
>> On Thursday, December 28, 2017 7:44 AM, Kishon Vijay Abraham I wrote:
>>>
>>> Hi Gustavo,
>>>
>>> On Thursday 28 December 2017 05:26 PM, Gustavo Pimentel wrote:
>>>> This patch adapts Keystone SoC specific driver to use the new interrupt
>>> api
>>>> available in pcie-designware. A new callback was added to
>>> dw_pcie_host_ops
>>>> to handle a specific Keystone function and msi_host_init callback is
>>>> changed to simplify the access to pci data structure for keystone all
>>> SoC
>>>> drivers that use the structure.
>>>>
>>>> Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
>>>> ---
>>>> Change v1->v2:
>>>> - Removed hardcoded num_vectors configuration (now it is done in the
>>> core driver by default)
>>>> Change v2->v3:
>>>> -
>>>>
>>>>
>>>>
>>>>
>>>>
>>>>  drivers/pci/dwc/pci-keystone-dw.c      | 88
>> ++---------------------------
>>> -----
>>>>  drivers/pci/dwc/pci-keystone.c         |  1 +
>>>>  drivers/pci/dwc/pci-keystone.h         |  4 +-
>>>>  drivers/pci/dwc/pci-layerscape.c       |  3 +-
>>>>  drivers/pci/dwc/pcie-designware-host.c | 19 ++++++--
>>>>  drivers/pci/dwc/pcie-designware.h      |  3 +-
>>>
>>> The designware specific patches should be part of
>>> "[1/9] pci: adding new irq api to pci-designware"
> 
> Ok, I will move your (Kishon) fixes to the 0001 patch file, no problem.
> 
>>>
>>> Also layerscap is not related to $subject.
> 
> Please note there are some initial changes on this patch (maybe they could be in
> a isolated patch) related to pci-layerscape.c, pcie-designware-host.c and
> pcie-designware.h files that changes the msi_host_init callback signature and
> this affects the Keystone, Layerscape drivers and the core at the same time,
> that's the reason why this modification touches on these three files and should
> be together.
> Was I able to pass this information clearly?

Got it. $subject or the commit message didn't have that information. However as
I've commented on your patch, it's better if we keep the signature of
msi_host_init as it is.

Thanks
Kishon

Re: [PATCH v3 0/9] add new irq api to pcie-designware

[Gustavo Pimentel]

Hi Bjorn,

On 28/12/2017 18:56, Bjorn Helgaas wrote:
> On Thu, Dec 28, 2017 at 11:56:38AM +0000, Gustavo Pimentel wrote:
>> This patch series adds the new interrupt api to pcie-designware make it
>> possible to use features like MSIX.
>> The work consisted of adapting the pcie-designware-host and each SoC
>> specific driver.
>> The patch set was made against the Bjorn' next branch.
>> A new patch set (v3) was created that includes Kishon's fixes (pci end
>> point error and a dra7xx warning) in file
>> 0007-pci-keystone-SoC-driver-adapted-to-new-irq-API.patch.
>>
>> Gustavo Pimentel (9):
>>   pci: adding new irq api to pci-designware
>>   pci: exynos SoC driver adapted to new irq API
>>   pci: imx6 SoC driver adapted to new irq API
>>   pci: artpec6 SoC driver adapted to new irq API
>>   pci: generic PCIe DW driver adapted to new irq API
>>   pci: qcom SoC driver adapted to new irq API
>>   pci: keystone SoC driver adapted to new irq API
>>   pci: removing old irq api from pcie-designware
>>   pci: remove limitation of the number of the available IRQs
> 
> Please update the summary lines to match the drivers/pci conventions:
> 
>   PCI: dwc: Add new IRQ API
>   PCI: dwc: exynos: Adapt to new IRQ API
>   PCI: dwc: imx6: Adapt to new IRQ API
>   PCI: dwc: artpec6: Adapt to new IRQ API
>   PCI: dwc: designware: Adapt to new IRQ API
>   PCI: dwc: qcom: Adapt to new IRQ API
>   PCI: dwc: keystone: Adapt to new IRQ API
>   PCI: dwc: Remove old IRQ API
>   PCI: dwc: Remove limitation on number of IRQs
> 
> The first patch summary should contain more information than "Add new
> IRQ API".  That summary doesn't tell us anything about what is new or
> why we want it.  Even the changelog doesn't contain that information.
> 
> Please also update the changelogs to consistently capitalize IRQ, API,
> etc.  It's currently a mix, which is distracting to read.
> 
> Also, instead of saying "This patch adds the ...", simply say "Add the
> ...".  The "This patch" context is obvious since the changelog is an
> integral part of the commit.
> 
> Please use blank lines to separate paragraphs.
> 

Ok, I'll do it like said. Thanks for the feedback.

>>  drivers/pci/dwc/pci-exynos.c           |  18 --
>>  drivers/pci/dwc/pci-imx6.c             |  18 --
>>  drivers/pci/dwc/pci-keystone-dw.c      |  88 +-------
>>  drivers/pci/dwc/pci-keystone.c         |   1 +
>>  drivers/pci/dwc/pci-keystone.h         |   4 +-
>>  drivers/pci/dwc/pci-layerscape.c       |   4 +-
>>  drivers/pci/dwc/pcie-artpec6.c         |  18 --
>>  drivers/pci/dwc/pcie-designware-host.c | 391 +++++++++++++++++++--------------
>>  drivers/pci/dwc/pcie-designware-plat.c |  16 --
>>  drivers/pci/dwc/pcie-designware.h      |  30 ++-
>>  drivers/pci/dwc/pcie-qcom.c            |  16 --
>>  11 files changed, 254 insertions(+), 350 deletions(-)
>>
>> -- 
>> 2.7.4
>>
>>

Re: [PATCH v3 1/9] pci: adding new irq api to pci-designware

[Gustavo Pimentel]

Hi Kishon,

On 29/12/2017 09:52, Kishon Vijay Abraham I wrote:
> Hi Gustavo,
> 
> On Thursday 28 December 2017 05:26 PM, Gustavo Pimentel wrote:
>> This patch adds the new interrupt api to pcie-designware, keeping the old
>> one. Although the old API is still available, pcie-designware initiates
>> with the new one.
>>
>> Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
>> ---
>> Change v1->v2:
>> - num_vectors is now not configurable by DT. Now it is 32 by default and
>> can be overridden by any specific SoC driver.
>> Change v2->v3:
>> - Nothing changed, just to follow the patch set version.
>>
>>  drivers/pci/dwc/pcie-designware-host.c | 282 +++++++++++++++++++++++++++++----
>>  drivers/pci/dwc/pcie-designware.h      |  17 ++
>>  2 files changed, 272 insertions(+), 27 deletions(-)
>>
>> diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
>> index 81e2157..289d476 100644
>> --- a/drivers/pci/dwc/pcie-designware-host.c
>> +++ b/drivers/pci/dwc/pcie-designware-host.c
>> @@ -11,6 +11,7 @@
>>   * published by the Free Software Foundation.
>>   */
>>  
>> +#include <linux/irqchip/chained_irq.h>
>>  #include <linux/irqdomain.h>
>>  #include <linux/of_address.h>
>>  #include <linux/of_pci.h>
>> @@ -53,6 +54,30 @@ static struct irq_chip dw_msi_irq_chip = {
>>  	.irq_unmask = pci_msi_unmask_irq,
>>  };
>>  
>> +static void dw_msi_mask_irq(struct irq_data *d)
>> +{
>> +	pci_msi_mask_irq(d);
>> +	irq_chip_mask_parent(d);
>> +}
>> +
>> +static void dw_msi_unmask_irq(struct irq_data *d)
>> +{
>> +	pci_msi_unmask_irq(d);
>> +	irq_chip_unmask_parent(d);
>> +}
>> +
>> +static struct irq_chip dw_pcie_msi_irq_chip = {
>> +	.name = "PCI-MSI",
>> +	.irq_mask = dw_msi_mask_irq,
>> +	.irq_unmask = dw_msi_unmask_irq,
>> +};
>> +
>> +static struct msi_domain_info dw_pcie_msi_domain_info = {
>> +	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
>> +		     MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI),
>> +	.chip	= &dw_pcie_msi_irq_chip,
>> +};
>> +
>>  /* MSI int handler */
>>  irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
>>  {
>> @@ -81,6 +106,191 @@ irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
>>  	return ret;
>>  }
>>  
>> +/* Chained MSI interrupt service routine */
>> +static void dw_chained_msi_isr(struct irq_desc *desc)
>> +{
>> +	struct irq_chip *chip = irq_desc_get_chip(desc);
>> +	struct pcie_port *pp;
>> +	struct dw_pcie *pci;
>> +
>> +	chained_irq_enter(chip, desc);
>> +	pci = irq_desc_get_handler_data(desc);
>> +	pp = &pci->pp;
>> +
>> +	dw_handle_msi_irq(pp);
>> +
>> +	chained_irq_exit(chip, desc);
>> +}
>> +
>> +static void dw_pci_setup_msi_msg(struct irq_data *data, struct msi_msg *msg)
>> +{
>> +	struct dw_pcie *pci = irq_data_get_irq_chip_data(data);
>> +	struct pcie_port *pp = &pci->pp;
>> +	u64 msi_target;
>> +
>> +	if (pp->ops->get_msi_addr)
>> +		msi_target = pp->ops->get_msi_addr(pp);
>> +	else
>> +		msi_target = virt_to_phys((void *)pp->msi_data);
>> +
>> +	msg->address_lo = lower_32_bits(msi_target);
>> +	msg->address_hi = upper_32_bits(msi_target);
>> +
>> +	if (pp->ops->get_msi_data)
>> +		msg->data = pp->ops->get_msi_data(pp, data->hwirq);
>> +	else
>> +		msg->data = data->hwirq;
>> +
>> +	dev_dbg(pci->dev, "msi#%d address_hi %#x address_lo %#x\n",
>> +		(int)data->hwirq, msg->address_hi, msg->address_lo);
>> +}
>> +
>> +static int dw_pci_msi_set_affinity(struct irq_data *irq_data,
>> +				   const struct cpumask *mask, bool force)
>> +{
>> +	return -EINVAL;
>> +}
>> +
>> +static void dw_pci_bottom_mask(struct irq_data *data)
>> +{
>> +	struct dw_pcie *pci = irq_data_get_irq_chip_data(data);
>> +	struct pcie_port *pp = &pci->pp;
>> +	unsigned int res, bit, ctrl;
>> +	unsigned long flags;
>> +
>> +	spin_lock_irqsave(&pp->lock, flags);
>> +
>> +	if (pp->ops->msi_clear_irq)
>> +		pp->ops->msi_clear_irq(pp, data->hwirq);
>> +	else {
>> +		ctrl = data->hwirq / 32;
>> +		res = ctrl * 12;
>> +		bit = data->hwirq % 32;
>> +
>> +		pp->irq_status[ctrl] &= ~(1 << bit);
>> +		dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4,
>> +				    pp->irq_status[ctrl]);
>> +	}
>> +
>> +	spin_unlock_irqrestore(&pp->lock, flags);
>> +}
>> +
>> +static void dw_pci_bottom_unmask(struct irq_data *data)
>> +{
>> +	struct dw_pcie *pci = irq_data_get_irq_chip_data(data);
>> +	struct pcie_port *pp = &pci->pp;
>> +	unsigned int res, bit, ctrl;
>> +	unsigned long flags;
>> +
>> +	spin_lock_irqsave(&pp->lock, flags);
>> +
>> +	if (pp->ops->msi_set_irq)
>> +		pp->ops->msi_set_irq(pp, data->hwirq);
>> +	else {
>> +		ctrl = data->hwirq / 32;
>> +		res = ctrl * 12;
>> +		bit = data->hwirq % 32;
>> +
>> +		pp->irq_status[ctrl] |= 1 << bit;
>> +		dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4,
>> +				    pp->irq_status[ctrl]);
>> +	}
>> +
>> +	spin_unlock_irqrestore(&pp->lock, flags);
>> +}
>> +
>> +static struct irq_chip dw_pci_msi_bottom_irq_chip = {
>> +	.name = "DWPCI-MSI",
>> +	.irq_compose_msi_msg = dw_pci_setup_msi_msg,
>> +	.irq_set_affinity = dw_pci_msi_set_affinity,
>> +	.irq_mask = dw_pci_bottom_mask,
>> +	.irq_unmask = dw_pci_bottom_unmask,
>> +};
>> +
>> +static int dw_pcie_irq_domain_alloc(struct irq_domain *domain,
>> +				    unsigned int virq, unsigned int nr_irqs,
>> +				    void *args)
>> +{
>> +	struct dw_pcie *pci = domain->host_data;
>> +	struct pcie_port *pp = &pci->pp;
>> +	unsigned long flags;
>> +	unsigned long bit;
>> +	u32 i;
>> +
>> +	spin_lock_irqsave(&pp->lock, flags);
>> +
>> +	bit = bitmap_find_next_zero_area(pp->msi_irq_in_use, pp->num_vectors, 0,
>> +					 nr_irqs, 0);
>> +
>> +	if (bit >= pp->num_vectors) {
>> +		spin_unlock_irqrestore(&pp->lock, flags);
>> +		return -ENOSPC;
>> +	}
>> +
>> +	bitmap_set(pp->msi_irq_in_use, bit, nr_irqs);
>> +
>> +	spin_unlock_irqrestore(&pp->lock, flags);
>> +
>> +	for (i = 0; i < nr_irqs; i++)
>> +		irq_domain_set_info(domain, virq + i, bit + i,
>> +				    &dw_pci_msi_bottom_irq_chip,
>> +				    domain->host_data, handle_simple_irq,
>> +				    NULL, NULL);
>> +
>> +	return 0;
>> +}
>> +
>> +static void dw_pcie_irq_domain_free(struct irq_domain *domain,
>> +				    unsigned int virq, unsigned int nr_irqs)
>> +{
>> +	struct irq_data *data = irq_domain_get_irq_data(domain, virq);
>> +	struct dw_pcie *pci = irq_data_get_irq_chip_data(data);
>> +	struct pcie_port *pp = &pci->pp;
>> +	unsigned long flags;
>> +
>> +	spin_lock_irqsave(&pp->lock, flags);
>> +	bitmap_clear(pp->msi_irq_in_use, data->hwirq, nr_irqs);
>> +	spin_unlock_irqrestore(&pp->lock, flags);
>> +}
>> +
>> +static const struct irq_domain_ops dw_pcie_msi_domain_ops = {
>> +	.alloc	= dw_pcie_irq_domain_alloc,
>> +	.free	= dw_pcie_irq_domain_free,
>> +};
>> +
>> +int dw_pcie_allocate_domains(struct dw_pcie *pci)
>> +{
> 
> Since this function is specific to host mode, the preferred argument should be
> struct pcie_port *pp.
> 
>> +	struct pcie_port *pp = &pci->pp;
>> +	struct fwnode_handle *fwnode = of_node_to_fwnode(pci->dev->of_node);
>> +
>> +	pp->irq_domain = irq_domain_create_linear(fwnode, pp->num_vectors,
>> +					       &dw_pcie_msi_domain_ops, pci);
> 
> pp can be directly passed as host_data so that getting pp again back from pci
> can be avoided in all the above functions.

Ok, I'll change it.
Thanks.

> 
> Thanks
> Kishon
> 

Re: [PATCH v3 7/9] pci: keystone SoC driver adapted to new irq API

[Gustavo Pimentel]

Hi Kishon,

On 29/12/2017 10:08, Kishon Vijay Abraham I wrote:
> Hi Gustavo,
> 
> On Thursday 28 December 2017 05:26 PM, Gustavo Pimentel wrote:
>> This patch adapts Keystone SoC specific driver to use the new interrupt api
>> available in pcie-designware. A new callback was added to dw_pcie_host_ops
>> to handle a specific Keystone function and msi_host_init callback is
>> changed to simplify the access to pci data structure for keystone all SoC
>> drivers that use the structure.
>>
>> Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
>> ---
>> Change v1->v2:
>> - Removed hardcoded num_vectors configuration (now it is done in the core driver by default)
>> Change v2->v3:
>> - 
>>
>>
>>
>>
>>
>>  drivers/pci/dwc/pci-keystone-dw.c      | 88 ++--------------------------------
>>  drivers/pci/dwc/pci-keystone.c         |  1 +
>>  drivers/pci/dwc/pci-keystone.h         |  4 +-
>>  drivers/pci/dwc/pci-layerscape.c       |  3 +-
>>  drivers/pci/dwc/pcie-designware-host.c | 19 ++++++--
>>  drivers/pci/dwc/pcie-designware.h      |  3 +-
>>  6 files changed, 26 insertions(+), 92 deletions(-)
>>
>> diff --git a/drivers/pci/dwc/pci-keystone-dw.c b/drivers/pci/dwc/pci-keystone-dw.c
>> index 2fb20b8..4fe4ab3 100644
>> --- a/drivers/pci/dwc/pci-keystone-dw.c
>> +++ b/drivers/pci/dwc/pci-keystone-dw.c
>> @@ -124,19 +124,15 @@ void ks_dw_pcie_handle_msi_irq(struct keystone_pcie *ks_pcie, int offset)
>>  	}
>>  }
>>  
>> -static void ks_dw_pcie_msi_irq_ack(struct irq_data *d)
>> +void ks_dw_pcie_msi_irq_ack(int irq, struct pcie_port *pp)
>>  {
>>  	u32 offset, reg_offset, bit_pos;
>>  	struct keystone_pcie *ks_pcie;
>> -	struct msi_desc *msi;
>> -	struct pcie_port *pp;
>>  	struct dw_pcie *pci;
>>  
>> -	msi = irq_data_get_msi_desc(d);
>> -	pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
>>  	pci = to_dw_pcie_from_pp(pp);
>>  	ks_pcie = to_keystone_pcie(pci);
>> -	offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
>> +	offset = irq - irq_linear_revmap(pp->irq_domain, 0);
>>  	update_reg_offset_bit_pos(offset, &reg_offset, &bit_pos);
>>  
>>  	ks_dw_app_writel(ks_pcie, MSI0_IRQ_STATUS + (reg_offset << 4),
>> @@ -166,85 +162,9 @@ void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq)
>>  			 BIT(bit_pos));
>>  }
>>  
>> -static void ks_dw_pcie_msi_irq_mask(struct irq_data *d)
>> +int ks_dw_pcie_msi_host_init(struct dw_pcie *pci, struct msi_controller *chip)
>>  {
>> -	struct msi_desc *msi;
>> -	struct pcie_port *pp;
>> -	u32 offset;
>> -
>> -	msi = irq_data_get_msi_desc(d);
>> -	pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
>> -	offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
>> -
>> -	/* Mask the end point if PVM implemented */
>> -	if (IS_ENABLED(CONFIG_PCI_MSI)) {
>> -		if (msi->msi_attrib.maskbit)
>> -			pci_msi_mask_irq(d);
>> -	}
>> -
>> -	ks_dw_pcie_msi_clear_irq(pp, offset);
>> -}
>> -
>> -static void ks_dw_pcie_msi_irq_unmask(struct irq_data *d)
>> -{
>> -	struct msi_desc *msi;
>> -	struct pcie_port *pp;
>> -	u32 offset;
>> -
>> -	msi = irq_data_get_msi_desc(d);
>> -	pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
>> -	offset = d->irq - irq_linear_revmap(pp->irq_domain, 0);
>> -
>> -	/* Mask the end point if PVM implemented */
>> -	if (IS_ENABLED(CONFIG_PCI_MSI)) {
>> -		if (msi->msi_attrib.maskbit)
>> -			pci_msi_unmask_irq(d);
>> -	}
>> -
>> -	ks_dw_pcie_msi_set_irq(pp, offset);
>> -}
>> -
>> -static struct irq_chip ks_dw_pcie_msi_irq_chip = {
>> -	.name = "Keystone-PCIe-MSI-IRQ",
>> -	.irq_ack = ks_dw_pcie_msi_irq_ack,
>> -	.irq_mask = ks_dw_pcie_msi_irq_mask,
>> -	.irq_unmask = ks_dw_pcie_msi_irq_unmask,
>> -};
>> -
>> -static int ks_dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
>> -			      irq_hw_number_t hwirq)
>> -{
>> -	irq_set_chip_and_handler(irq, &ks_dw_pcie_msi_irq_chip,
>> -				 handle_level_irq);
>> -	irq_set_chip_data(irq, domain->host_data);
>> -
>> -	return 0;
>> -}
>> -
>> -static const struct irq_domain_ops ks_dw_pcie_msi_domain_ops = {
>> -	.map = ks_dw_pcie_msi_map,
>> -};
>> -
>> -int ks_dw_pcie_msi_host_init(struct pcie_port *pp, struct msi_controller *chip)
>> -{
>> -	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>> -	struct keystone_pcie *ks_pcie = to_keystone_pcie(pci);
>> -	struct device *dev = pci->dev;
>> -	int i;
>> -
>> -	pp->irq_domain = irq_domain_add_linear(ks_pcie->msi_intc_np,
>> -					MAX_MSI_IRQS,
>> -					&ks_dw_pcie_msi_domain_ops,
>> -					chip);
>> -	if (!pp->irq_domain) {
>> -		dev_err(dev, "irq domain init failed\n");
>> -		return -ENXIO;
>> -	}
>> -
>> -	for (i = 0; i < MAX_MSI_IRQS; i++)
>> -		irq_create_mapping(pp->irq_domain, i);
>> -
>> -	return 0;
>> +	return dw_pcie_allocate_domains(pci);
>>  }
>>  
>>  void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie *ks_pcie)
>> diff --git a/drivers/pci/dwc/pci-keystone.c b/drivers/pci/dwc/pci-keystone.c
>> index 5bee3af..76901fa 100644
>> --- a/drivers/pci/dwc/pci-keystone.c
>> +++ b/drivers/pci/dwc/pci-keystone.c
>> @@ -297,6 +297,7 @@ static const struct dw_pcie_host_ops keystone_pcie_host_ops = {
>>  	.msi_clear_irq = ks_dw_pcie_msi_clear_irq,
>>  	.get_msi_addr = ks_dw_pcie_get_msi_addr,
>>  	.msi_host_init = ks_dw_pcie_msi_host_init,
>> +	.msi_irq_ack = ks_dw_pcie_msi_irq_ack,
>>  	.scan_bus = ks_dw_pcie_v3_65_scan_bus,
>>  };
>>  
>> diff --git a/drivers/pci/dwc/pci-keystone.h b/drivers/pci/dwc/pci-keystone.h
>> index 30b7bc2..04e1366 100644
>> --- a/drivers/pci/dwc/pci-keystone.h
>> +++ b/drivers/pci/dwc/pci-keystone.h
>> @@ -53,9 +53,9 @@ int ks_dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
>>  		unsigned int devfn, int where, int size, u32 *val);
>>  void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie);
>>  void ks_dw_pcie_initiate_link_train(struct keystone_pcie *ks_pcie);
>> +void ks_dw_pcie_msi_irq_ack(int i, struct pcie_port *pp);
>>  void ks_dw_pcie_msi_set_irq(struct pcie_port *pp, int irq);
>>  void ks_dw_pcie_msi_clear_irq(struct pcie_port *pp, int irq);
>>  void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp);
>> -int ks_dw_pcie_msi_host_init(struct pcie_port *pp,
>> -		struct msi_controller *chip);
>> +int ks_dw_pcie_msi_host_init(struct dw_pcie *pci, struct msi_controller *chip);
>>  int ks_dw_pcie_link_up(struct dw_pcie *pci);
>> diff --git a/drivers/pci/dwc/pci-layerscape.c b/drivers/pci/dwc/pci-layerscape.c
>> index 8f34c2f..cb9af93e3 100644
>> --- a/drivers/pci/dwc/pci-layerscape.c
>> +++ b/drivers/pci/dwc/pci-layerscape.c
>> @@ -185,10 +185,9 @@ static int ls1021_pcie_host_init(struct pcie_port *pp)
>>  	return ls_pcie_host_init(pp);
>>  }
>>  
>> -static int ls_pcie_msi_host_init(struct pcie_port *pp,
>> +static int ls_pcie_msi_host_init(struct dw_pcie *pci,
>>  				 struct msi_controller *chip)
>>  {
>> -	struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
>>  	struct device *dev = pci->dev;
>>  	struct device_node *np = dev->of_node;
>>  	struct device_node *msi_node;
>> diff --git a/drivers/pci/dwc/pcie-designware-host.c b/drivers/pci/dwc/pcie-designware-host.c
>> index 289d476..ee1c105 100644
>> --- a/drivers/pci/dwc/pcie-designware-host.c
>> +++ b/drivers/pci/dwc/pcie-designware-host.c
>> @@ -66,8 +66,20 @@ static void dw_msi_unmask_irq(struct irq_data *d)
>>  	irq_chip_unmask_parent(d);
>>  }
>>  
>> +static void dw_pci_ack_irq(struct irq_data *d)
>> +{
>> +	struct msi_desc *msi = irq_data_get_msi_desc(d);
>> +	struct pcie_port *pp;
>> +
>> +	pp = (struct pcie_port *) msi_desc_to_pci_sysdata(msi);
>> +
>> +	if (pp->ops->msi_irq_ack)
>> +		pp->ops->msi_irq_ack(d->irq, pp);
>> +}
>> +
>>  static struct irq_chip dw_pcie_msi_irq_chip = {
>>  	.name = "PCI-MSI",
>> +	.irq_ack = dw_pci_ack_irq,
>>  	.irq_mask = dw_msi_mask_irq,
>>  	.irq_unmask = dw_msi_unmask_irq,
>>  };
>> @@ -234,7 +246,7 @@ static int dw_pcie_irq_domain_alloc(struct irq_domain *domain,
>>  	for (i = 0; i < nr_irqs; i++)
>>  		irq_domain_set_info(domain, virq + i, bit + i,
>>  				    &dw_pci_msi_bottom_irq_chip,
>> -				    domain->host_data, handle_simple_irq,
>> +				    domain->host_data, handle_level_irq,
>>  				    NULL, NULL);
>>  
>>  	return 0;
>> @@ -619,11 +631,12 @@ int dw_pcie_host_init(struct pcie_port *pp)
>>  			if (ret)
>>  				goto error;
>>  
>> -			irq_set_chained_handler_and_data(pci->pp.msi_irq,
>> +			if (pp->msi_irq)
>> +				irq_set_chained_handler_and_data(pp->msi_irq,
>>  							 dw_chained_msi_isr,
>>  							 pci);
>>  		} else {
>> -			ret = pp->ops->msi_host_init(pp, &dw_pcie_msi_chip);
>> +			ret = pp->ops->msi_host_init(pci, &dw_pcie_msi_chip);
>>  			if (ret < 0)
>>  				goto error;
>>  		}
>> diff --git a/drivers/pci/dwc/pcie-designware.h b/drivers/pci/dwc/pcie-designware.h
>> index 6178251..5294352 100644
>> --- a/drivers/pci/dwc/pcie-designware.h
>> +++ b/drivers/pci/dwc/pcie-designware.h
>> @@ -145,7 +145,8 @@ struct dw_pcie_host_ops {
>>  	u32 (*get_msi_data)(struct pcie_port *pp, int pos);
>>  	void (*scan_bus)(struct pcie_port *pp);
>>  	void (*set_num_vectors)(struct pcie_port *pp);
>> -	int (*msi_host_init)(struct pcie_port *pp, struct msi_controller *chip);
>> +	int (*msi_host_init)(struct dw_pcie *pci, struct msi_controller *chip);
> 
> I'd prefer the signature is maintained since msi_host_init being a host
> specific callback, it makes sense to have "struct pcie_port *pp".

Ok, I'll revert and adapt it.
Thanks.

> 
> Thanks
> Kishon
>